Re: async clk input, clock glitches


"Antti" <Antti.Lukats@xxxxxxxxxxxxxx> wrote in message
news:860e9a98-ef7c-4228-b5d8-ee2c44c95054@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
On 29 Mrz., 20:34, Mike Treseler <mike_trese...@xxxxxxxxxxx> wrote:
Antti wrote:
any ideas how to really clean the 4mhz clock?

I would try soldering on one of those
little schmitt trigger packs. Sometimes
a low slew rate will clock both edges
once in a while.

-- Mike Treseler

yes schmit trigger input could be the cure..
but i still cant understand the missing clock pulses!

Antti

Your post never mentioned anything about having measured a slow edge on the
4MHz signal either. If the edge rate is within spec, adding a Schmitt
trigger will have no effect. Have you taken a scope to that signal and
measured the edge rate?

Kevin Jennings


.

Relevant Pages

  • Re: XIlinx Spartan 2E stuck in configuration mode
    ... without adding a multi-output clock buffer and star-routing the CCLKs. ... Why is a schmitt trigger input an automatic cure for SI issues? ... the reflections and improper termination of transmission lines, ... As the FPGAs get ever-faster, they get LESS tolerant of slow edges, ...
    (comp.arch.fpga)
  • Re: async clk input, clock glitches
    ... little schmitt trigger packs. ... a low slew rate will clock both edges ... -- Mike Treseler ... but i still cant understand the missing clock pulses! ...
    (comp.arch.fpga)
  • Re: Looking for two-input comparator with hysteresis
    ... Any old fool can tap into that transformer to pulse a Schmitt trigger or comparator or what have you, but tapping into the timing in such a way that the resulting reference clock is not cumulatively "pulled" by the DC loading of the circuit or mains variation is an entirely different story. ... You are trapped into thinking about steady state. ... Therefore it will accumulate error. ...
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  • Re: Looking for two-input comparator with hysteresis
    ... Any old fool can tap into that transformer to pulse a Schmitt trigger or ... that the resulting reference clock is not cumulatively "pulled" by the ... If the schmitt is squaring up 60 Hz cycles, ... exactly once (not zero times, and not twice) where's the error? ...
    (sci.electronics.design)
  • Re: async clk input, clock glitches
    ... a low slew rate will clock both edges ... but i still cant understand the missing clock pulses! ... If the edge rate is within spec, adding a Schmitt trigger will have no effect. ...
    (comp.arch.fpga)