Re: async clk input, clock glitches

Antti wrote:

the timing analyze with actel FPGA is something so:so, I have seen a
shift register clocked at 4mhz working 100% when FPGA utilization
below 90% and failing 100% when FPGA utilization over 90%, without any
problem reported by the timing tools or post place simulation. I wasnt
belive my eyes when i did see that, but so it was. Later i found some
actel appnote about methods of dealing with such cases. I hoped that
actel tools take of such situations but they do not.

That may not be a 'tools' problem at all, but could be a real hardware
issue. It is unlikely their test coverage is that great in
such 'corner cases' - most vendors expect you to go to a larger device
when you hit 90% ! :)

As more and more of the device is active, the ground noise and crosstalk has to get steadily worse - what external loads is the device driving, and what package ?.

I get the impression this was part of the driving force behind the flip-chip-bga and all-die-bondpads

-jg

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