Re: async clk input, clock glitches

On Mar 29, 10:42 am, mk <kal*@dspia.*comdelete> wrote:
On Sat, 29 Mar 2008 10:00:50 -0700 (PDT), Peter Alfke

<al...@xxxxxxxxxxxxx> wrote:
Antti, click on

http://www.nalanda.nitc.ac.in/industry/appnotes/xilinx/documents/xcel...

which shows two different ways to avoid the effect of double-edges on
a clock.
I wrote that many years ago, and published it in Xilinx XCell magazine
#34
Peter Alfke

I think it's highly humorous for a Xilinx employee to post a link to a
university in India for a document which Xilinx has created but unable
to archive apparently.

Not so strange when the Xilinx employee (and incidentally also the
author of the article) is at home and in a hurry, and just googles for
the first hit.
Who cares about geography in the age of the internet...
Peter Alfke
.