Re: async clk input, clock glitches

On 29 Mrz., 18:00, Peter Alfke <al...@xxxxxxxxxxxxx> wrote:
On Mar 29, 2:41 am, Antti <Antti.Luk...@xxxxxxxxxxxxxx> wrote:



Hi

FPGA has
1) 50mhz system clock from ext oscillator
2) 4Mhz clk that is async to the 50mhz

problem, the 4MHz clk input sees double clk pulse, error rate
approximate 1 to 10.000.000
unfortunatly the 4mhz clock needs to be used inside without phase
delay, so oversampling and filtering with 50mhz is not an option,
unless using very clever no delay glitch surpression filter

external small R/C circuit on 5mhz doesnt change the error rate much,
ah currently the 4mhz is clocked 1 time with 50mhz, this seemed to
give better results as using the 4mhz clock directly

any ideas how to really clean the 4mhz clock?
or any thumb guess what is the likeliness to see double clk edges when
sampling 4mhz with async 50mhz?
could the "error rate" of such sampling be that 1:10M what I am
seeing?

I assume the 4 mhz clock is rather good, it coming from an ASIC and
has total wire lenght from asic to FPGA maybe 20 mm (but over PCB edge
connector). I did kinda think its hard to belive that the clock edge
is so slow or noisy that 50mhz sampling could ever see double/wrong
edges but guess i am wrong

it doesnt seem to be cross talk either, as there arent much IOs
toggling at all

hm it looks like in rare cases the error is also one clock pulse
missing!

:) any good suggestions are welcome, how to troubleshoot the issue

unfortunatly the FPGA is actel so can use any on-chip logic analyzer
core, and the chip is rather full also, some internal signal could be
routed out to external logic analyzer though if badly needed, but so
far i am trying to fix the issue by thinking, and error-retry...

Antti

Antti, click on

http://www.nalanda.nitc.ac.in/industry/appnotes/xilinx/documents/xcel...

which shows two different ways to avoid the effect of double-edges on
a clock.
I wrote that many years ago, and published it in Xilinx XCell magazine
#34
Peter Alfke

Hi Peter,

thanks I do know those things think also but i still printed the xcell
pages out :)
now, in Xilinx FPGA I dont see the problem :)
but the final target is actel FPGA (because: cost+security+package)
and in Actel i see both double and missing clocks

so i am still puzzled, there must be something very basic bad thing
somewhere

Antti















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