Re: implementing ethernet FCS code in verilog
- From: sky465nm@xxxxxxxxxxx
- Date: Mon, 17 Mar 2008 10:04:08 +0100 (CET)
Dilan <dilan2005@xxxxxxxxx> wrote:
hi,
i am going to use easics tool for generating crc32 verilog code
(8bit input) (www.easics.com/webtools/crctool) . i was able to
implement correctly.but i need more info to how use this crc to
generate FCS of a ethernet packt.
i heard about there must be some bit reversal before applying to crc
generator. but i am not clear about it .can any one guide me to what
have to data stream before applying to crc and when checksum created
if further processing had to be done on checksum
The crc you need to apply is the CRC32 AUTODIN II. This is to be applied to
all bits after the frame start. In 10/100M ethernet each 4-bits is in
reverse order (low nibble - high nibble). So you may need to swap these
before feeding the bits to the crc32 generator.
A C example of this crc is at:
http://darwinsource.opendarwin.org/10.3/text_cmds-30/cksum/crc32.c
You can use it for verification this way:
cat pktdata | cksum -o 3 | perl -ne 'if( /^(\d+)/ ){ printf("%08X\n",$1); }'
A tip is to capture some packets and use them as reference to verify your
crc is correct. Watch out for the order of bits coming out of the crc
generator aswell, sometimes these may need swapping aswell.
A quick way to find accidential bit swaps is to display the number in
binrary like this: perl -e 'printf("%032b\n",2);'
Hope this helps you a bit.
.
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