Re: Preventing optimization in cross clock domain logic

On Feb 29, 10:00 am, "Symon" <symon_bre...@xxxxxxxxxxx> wrote:

   |------- Metastable -------|
            __________
           |          |                        _____
   |------O| inverter |-------|---------------|     | Pulse
   |       |__________|       |               | XOR |---->
   |    ______       ______   |   ______   |--|_____| Out
   |   |      |     |      |  |  |      |  |
   |---| D  Q |-----| D  Q |--|--| D  Q |--|
Strobe |      |     |      |     |      |
/Clock |      |     |      |     |      |
-------|>     |  ---|>     | |---|>     |
       |______|  |  |______| |   |______|
                 |           |
                 |___________|___________  Output Clock

The pulse out should be clean by the next clock edge as long as the
routing is kept short.  Or if the clock period is very short another FF
can be added to feed the other leg of the XOR gate and assure a clean
output.

Thanks for that Symon -

checking the RTL schematic synthesized from my VHDL, the above seems
to be what I've ended up with, albeit with extra registers on input
and output, which are probably superfluous and just adding delay!

Best, Tom.

.