How to use xilinx specific features from Modelsim Designer 6.3a VHDL



Hi All,

I have started a test design in Modelsim Designer. I now have one entity
written in VHDL and have placed this entity on a block diagram and added
in- and out ports to the entity's signals. The entity simulates OK in a
testbench and synthesis is OK (no constraints but 100MHz clock given).

Placing all signals on an I/O pin is easy with the PACE tool for 'normal'
signals. But I can't figure out how to use a bi-directional differential
buffer.

My entity has 3 signals for use with this buffer: in, out, output_enable
And I want to connect these signals to a Bus-LVDS I/O buffer, but how?
Preferrably also using the input synchronization.

Next problem is the clock input. There's a 50MHz oscillator connected to
a clock input and I want to use the DCM to create a 100MHz (or even a
150MHz) global clock off of that.

I've searched the web and the Mentor and Xilinx sites, but found nothing
yet. Any hints how to do this or where to look for more information?

The Modelsim manuals are reasonable upto and including the simulation,
but fail after that. I know the synthesis and P&R are actually performed
by Xilinx tools, but they could have made an effort taking you through
the whole process as the offer complete integration. Or did I overlook
some manual or tutorial?

Xilinx on the other hand, only document the ISE design route, so it
seems I'm stuck somewhere in the middle.

First goal is to get the design running on the S3E starter kit.


--
Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)

"Computers in the future may weigh no more than 1.5 tons."
(Popular Mechanics, 1949)
.