Re: From ASIC RTL to FPGA, what are the things I should take care of?
- From: Ralf Hildebrandt <Ralf-Hildebrandt@xxxxxx>
- Date: Wed, 20 Feb 2008 21:45:29 +0100
jasonL schrieb:
I have a project to prototype an ASIC design on FPGA. What are the
things I should do? Here is some of my concerns:
Well .. good HDL code should be portable. ;-)
1) I understand FPGAs usually have 4 look-up table. Should I rewrite
the ASIC combinational logics to be four-inputs logics to improve the
utilization of FPGA?
No. Usually the FPGA is big enough. This is an advanced topic for
highly-optimized designs.
2) Netting if and case statements over three layers might results a
poor synthesis result in FPGA . Should I changes those netting codes
in ASIC RTL?
Flipflops are free in FPGAs. Therefore you can pipeline your design
easily. The only disadvantage are the additional clocks through the
pipeline.
3) ASIC synthesis need to generate clock tree and power rails. In FPGA
synthesis, Maybe I not need to care too much about it?
Ususally you should place an instance of a component, that tells the
synthesis tool to use global clocks and global signals for reset. For
Xilinx this it a BUFG.
4) Is there a to-do-list for this kind of job?
Usually I replace memories with BlockRAM inside the FPGA and use
instances of clock buffers. Thats it.
Fully synchronous designs are easily done on FPGAs, but even highly
clock-gated designs using a lot of latches run quite fine.
Ralf
.
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