Re: Possible CRC error on XC3S400 - now what?





Gabor wrote:
On Feb 5, 9:56 am, Michael Meeuwisse
<mickeymeeuw@nospamplease_thesearchcompanywithcolorfulletters'emailservice.com>
wrote:

Hi,



Sky46...@xxxxxxxxxxx wrote:

Michael Meeuwisse <mickeymeeuw@nospamplease_thesearchcompanywithcolorfulletters'emailservice.com> wrote:

I'm trying to configure a Xilinx Spartan 3 s400 through JTAG in a new
prototype but I'm getting some weird results back while programming it.
I hope somebody with more experience can help me out.

The fpga is the 2nd device in a chain of 3 devices, of which the third a
XC95144XL is which can be programmed succesfully. I assume therefore
that there are acceptable noise levels on the bus and bus speed
(currently at about ~1.2MHz - depends a bit on how fast the programmer
can handle incoming data but not faster than that) is Ok.

* Check power for any dips or transients.

My VccAux seems to be 2.34V, this is supplied by a lm1086-2.5 so I don't
really know what's causing this (it's just below the minimum required,
isn't it?) or how I can fix it. Vcco is 3.34V and VccInt is 1.20V.


* Connect directly with a parallell port jtag adapter.
Like this:http://www.xilinx.com/support/programr/jtag_cable.pdf

(And only try the USB approch once it confirmed to work)

The thing is, the programmer is embedded on the board itself so
connecting a different programmer would require me to start cutting pcb
traces.


* Lower the clocking frequency, try 50 kHz.

Didn't seem to help. Afaik there's no minimum clock so I even tried it
at ~100Hz (which takes forever btw, in case you never tried it) but it
still failed.


* Double check all pins related to configuration (DONE, M0,M1,M2, INIT_B,
CCLK, etc)

M[2:0] are all tied to ground, and changing this would again require
some force so I'd rather not. This shouldn't matter afaik, since you can
always program using JTAG anyway, right? Likewise, when configuring
using JTAG it doesn't matter what CCLK is, does it? I mentioned the
state of INIT_B, PROG_B and DONE earlier.


* You could connect pins to the fpga DIN etc.. back to your PC to verify your
fpga actually get the data you expect.

Would data pushed in through JTAG appear on DIN? I could write something
that checks TDO but I'm told the spartan spits out zeroes or other
nonsense when I'm shifting data in.

Thorsten Trenz wrote:

> Hi,
>
> Try to switch the modepins to JTAG only. Do you use a PC3 clone? There
> seems to be some problems in certain impact versions with PC3 and S3 if
> the chip is not in JTAG only mode.

The programmer is an FTDI FT2232 using an homebrew XSVF parser. I
believe I've got all the bugs worked out of the software since
programming the CPLD goes without a problem.

Cheers,

Mikehttp://projectvga.org


You didn't say what the first device in the chain was. There are
known
issues when placing a PlatformFlash (XCF02S for instance) in front of
a Spartan device wired up for master serial configuration mode.


Yeah sorry, it's a XCF04S. I've got some other issues with that one however, it seems that is has some dead banks which is why I'm trying to program the fpga directly in the first place. As far as I can tell these two problems are unrelated.

Do you have a pullup on the DONE pin? If not have you checked the
"Drive Done pin high" option in bitgen?


No, no external pull up. I've set "Configuration pin done" to Float and checked "Drive done pin high" as suggested by table 2.6 of ug332.

Are you providing enough clocks at the end of the bitstream load to
start up the device (again look at where DONE is supposed to go high
in the bitgen options)?


I think so, I've tried programming the CPLD after I attempted to program the FPGA which should provide plenty of clock cycles, but it didn't change anything.

That's all I can think of.

By the way if you are using an XFCxxS device in front of your FPGA,
try erasing it to see if that helps the JTAG load.

Regards,
Gabor

As it turns out, the LM1086-2.5 needs a minimum of 4V and I'm only giving it 3.3V so that might be cause of some of the trouble - it certainly explains why my VccAux is only ~2.3V. I'm going to fix that now and hopefully it'll help.

Cheers,

Mike
http://projectvga.org
.



Relevant Pages

  • Re: Looking for consultant
    ... FPGA will have problems loading core. ... Sometimes it will load core, ... device when programming through JTAG. ...
    (sci.electronics.design)
  • Re: Verification errors using Xilinx Spartan 3E board
    ... I get some of the signals to not even be "connected" on the ... Try setting the FPGA Mode jumpers to JTAG. ... reported problems to me doing JTAG configurations on these boards when the ... This kind of errors however should yield to Programming error, ...
    (comp.arch.fpga)
  • JTAG in-system programming of PROM devices
    ... I've a question regarding in-system programming of prom devices using ... the JTAG protocol. ... XILINX Impact tool and the corresponding BSDL-file based informations. ... so called 'Instruction Capture Values' as part of the 'Instruction Scan ...
    (comp.arch.fpga)
  • Re: bootstrap mode for Motorola Coldfire MCF5206?
    ... For a ready-to-run and easy-to-use solution, you can look at P&E Micro, which includes software, but costs a little more. ... Many micros have a JTAG with "secret" registers for debugging and programming - I'd classify these along with Freescale's BDM interface. ... Why are they doing it is another matter (the profits JTAG toolvendors make are negligible for big silicon manufacturers). ...
    (comp.arch.embedded)
  • Re: Xilinx 3E design programs fine with 500E but fails with 250E
    ... programming over JTAG using the Impact SPI flash core. ... SPI programming can be found in the newer Xilinx SPI ... " The jumper on the Mpin is an enhancement for prototyping ...
    (comp.arch.fpga)