comp.arch.fpga

• Date Index

• Need info on systolic arrays in actual use, Marc Reinig
  • Re: Need info on systolic arrays in actual use, Kolja Sulimma
    • Re: Need info on systolic arrays in actual use, Marc Reinig
• DSP Ip Core, Jean-sébastien LEROY
• Is there any way to disable JTAG for Sptantan3AN, Goli
  • Re: Is there any way to disable JTAG for Sptantan3AN, Antti
  • Re: Is there any way to disable JTAG for Sptantan3AN, job
    • Re: Is there any way to disable JTAG for Sptantan3AN, waltherz
      • Re: Is there any way to disable JTAG for Sptantan3AN, Antti
• What demokit and VHDL compiler pair to buy, LM
  • Re: What demokit and VHDL compiler pair to buy, Dwayne Dilbeck
  • <Possible follow-ups>
  • Re: What demokit and VHDL compiler pair to buy, LM
• Re: CPLD Pad File, akshat
• Software for FPGA-based PC scope, Vagant
  • Re: Software for FPGA-based PC scope, Phil Hays
  • Re: Software for FPGA-based PC scope, sky465nm
    • Re: Software for FPGA-based PC scope, MikeShepherd564
    • Re: Software for FPGA-based PC scope, MikeShepherd564
• DCM Simulation : Input Clock Cycle Jitter, moogyd
  • Re: DCM Simulation : Input Clock Cycle Jitter, Symon
  • Re: DCM Simulation : Input Clock Cycle Jitter, job
• DSP newbie, FPGA
  • <Possible follow-ups>
  • Re: DSP newbie, RCIngham
• Making changes to custom IP in EDK, etorkild
  • Re: Making changes to custom IP in EDK, chakra
  • Re: Making changes to custom IP in EDK, Jeff Cunningham
  • Re: Making changes to custom IP in EDK, Guy Eschemann
    • Re: Making changes to custom IP in EDK, Skogul
      • Re: Making changes to custom IP in EDK, benradu
• sd card slave interface, bjzhangwn@xxxxxxxxx
  • Re: sd card slave interface, MikeShepherd564
  • <Possible follow-ups>
  • sd card slave interface, bjzhangwn@xxxxxxxxx
    • Re: sd card slave interface, Antti
• Using dma_sg_v2_01_a component with plb_ipif, Rajeev
• Bus2IP_WR/RDCE XIO_Out/in32 EDK 9.1, chakra
• Quicksim/modelsim, martstev
  • Re: Quicksim/modelsim, Jonathan Bromley
• ICAP attached to Microblaze on Virtex 2-pro.., Xesium
• Why must a V4 be configured within 10 minutes of power up?, Jeff Cunningham
  • Re: Why must a V4 be configured within 10 minutes of power up?, Symon
  • Re: Why must a V4 be configured within 10 minutes of power up?, austin
    • Re: Why must a V4 be configured within 10 minutes of power up?, MM
      • Re: Why must a V4 be configured within 10 minutes of power up?, austin
      • Re: Why must a V4 be configured within 10 minutes of power up?, MM
• Re: ANNC: ADC to FPGA Interface Webcast, sky465nm
  • Re: ANNC: ADC to FPGA Interface Webcast, bart
• Xilinx's microblaze hangs when a timer interrupt occurs after a "rand()" instruction., thomasrt2008
  • Re: Xilinx's microblaze hangs when a timer interrupt occurs after a "rand()" instruction., Jacob Schaffner
    • Re: Xilinx's microblaze hangs when a timer interrupt occurs after a "rand()" instruction., Remy . thomas . 38
• Tomorrow at Embeded in Nurnberg: Portable XSVF player demo, Antti
• SPI indirect programming using spartan 3e, kislo
  • Re: SPI indirect programming using spartan 3e, Antti
    • Re: SPI indirect programming using spartan 3e, Bryan
      • Re: SPI indirect programming using spartan 3e, Antti
• How to connect FPGA to a ASIC Board?, harisrini
  • Re: How to connect FPGA to a ASIC Board?, Antti
    • Re: How to connect FPGA to a ASIC Board?, Jonathan Bromley
      • Re: How to connect FPGA to a ASIC Board?, Antti
      • Re: How to connect FPGA to a ASIC Board?, Tim (one of many)
      • Re: How to connect FPGA to a ASIC Board?, Eric Smith
      • Re: How to connect FPGA to a ASIC Board?, mk
  • Re: How to connect FPGA to a ASIC Board?, comp.arch.fpga
• Viewing RTL schematic in Xilinx ISE, Stef
  • Re: Viewing RTL schematic in Xilinx ISE, randallchaas
    • Re: Viewing RTL schematic in Xilinx ISE, Stef
• OPB_MDM as UART in a PowerPC design, Pablo
• Preventing optimization in cross clock domain logic, Tom
  • Re: Preventing optimization in cross clock domain logic, rickman
    • Re: Preventing optimization in cross clock domain logic, Tom
      • Re: Preventing optimization in cross clock domain logic, rickman
      • Re: Preventing optimization in cross clock domain logic, Tom
  • Re: Preventing optimization in cross clock domain logic, Symon
    • Re: Preventing optimization in cross clock domain logic, Tom
• Convert some table into combinatorial circuit + optimization, sdf
  • Re: Convert some table into combinatorial circuit + optimization, Dwayne Dilbeck
    • Re: Convert some table into combinatorial circuit + optimization, Dwayne Dilbeck
    • Re: Convert some table into combinatorial circuit + optimization, sdf
      • Re: Convert some table into combinatorial circuit + optimization, Dwayne Dilbeck
      • Re: Convert some table into combinatorial circuit + optimization, Jim Granville
• ModelSim Natural arg value is negative, Brad Smallridge
  • Re: ModelSim Natural arg value is negative, Jonathan Bromley
    • Re: ModelSim Natural arg value is negative, Brad Smallridge
• set_input_delay min and max (timequest), Dolphin
  • Re: set_input_delay min and max (timequest), Gianluigi
• Re: Synthesis of functions in Quartus, RCIngham
• Typical jitter of high frequency oscillators?, Andreas Ehliar
  • Re: Typical jitter of high frequency oscillators?, austin
    • Re: Typical jitter of high frequency oscillators?, Symon
      • Re: Typical jitter of high frequency oscillators?, austin
    • Re: Typical jitter of high frequency oscillators?, Andreas Ehliar
  • Re: Typical jitter of high frequency oscillators?, John Larkin
• Using ICAP in s3a to reconfigure, kundanmit
  • Re: Using ICAP in s3a to reconfigure, Bryan
• Hardware Cosim no output, hilo_pupu
• Does Altera has some analogous file like XDL of Xilinx?, 傻瓜
  • Re: Does Altera has some analogous file like XDL of Xilinx?, George
    • Re: Does Altera has some analogous file like XDL of Xilinx?, antti . tyrvainen
      • Re: Does Altera has some analogous file like XDL of Xilinx?, George
• sFPDP IP Core, y_mh
• Re: Seed Values, FPGA
  • <Possible follow-ups>
  • Re: Seed Values, FPGA
    • Re: Seed Values, Mike Treseler
    • Re: Seed Values, Jim Lewis
      • Re: Seed Values, FPGA
      • Re: Seed Values, Mike Treseler
  • Re: Seed Values, FPGA
• Xilinx parallel cable 4 clone, aravind
  • Re: Xilinx parallel cable 4 clone, John_H
  • Re: Xilinx parallel cable 4 clone, Antti
  • Re: Xilinx parallel cable 4 clone, John Adair
• About John Williams' ICAP driver?, grant0920
  • Re: About John Williams' ICAP driver?, John Williams
• Picoblaze enhencement and assembler, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
  • Re: Picoblaze enhencement and assembler, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
  • Re: Picoblaze enhencement and assembler, Andrew Greensted
    • Re: Picoblaze enhencement and assembler, Paul Urbanus
      • Re: Picoblaze enhencement and assembler, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
    • Re: Picoblaze enhencement and assembler, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
  • Re: Picoblaze enhencement and assembler, Jim Granville
    • Re: Picoblaze enhencement and assembler, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
      • Re: Picoblaze enhencement and assembler, Nico Coesel
      • Re: Picoblaze enhencement and assembler, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
      • Re: Picoblaze enhencement and assembler, Nico Coesel
      • Re: Picoblaze enhencement and assembler, Mark
      • Re: Picoblaze enhencement and assembler, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
      • Re: Picoblaze enhencement and assembler, Gerhard Hoffmann
      • Re: Picoblaze enhencement and assembler, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
  • Re: Picoblaze enhencement and assembler, rickman
  • <Possible follow-ups>
  • Re: Picoblaze enhencement and assembler, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
• Re: Online Engineering Calculator Tool for Electronic Engineers - FREE to use, MikeShepherd564
• The Java processor JOP is now GPL, Martin Schoeberl
• Command to unzip hardware cosim files, hilo_pupu
• XEM3010, raullim7
• canny edge detection, saran
  • Re: canny edge detection, Jonathan Bromley
  • <Possible follow-ups>
  • canny edge detection, saran
• Planahead IP export, PatC
  • Re: Planahead IP export, brian . jackson
• FPGA Editor Tutorial based on examples, maverick
  • Re: FPGA Editor Tutorial based on examples, Frank Buss
  • Re: FPGA Editor Tutorial based on examples, MikeShepherd564
    • Re: FPGA Editor Tutorial based on examples, Frank Buss
    • Re: FPGA Editor Tutorial based on examples, sky465nm
  • Re: FPGA Editor Tutorial based on examples, Thorsten Kiefer
• Xilinx DCM for frequency synthesis -- newbie question, Bob Smith
  • Re: Xilinx DCM for frequency synthesis -- newbie question, morphiend
    • Re: Xilinx DCM for frequency synthesis -- newbie question, Bob Smith
      • Re: Xilinx DCM for frequency synthesis -- newbie question, PatC
  • Re: Xilinx DCM for frequency synthesis -- newbie question, JK
    • Re: Xilinx DCM for frequency synthesis -- newbie question, Bob Smith
      • Re: Xilinx DCM for frequency synthesis -- newbie question, mng
      • Re: Xilinx DCM for frequency synthesis -- newbie question, Bob Smith
      • Re: Xilinx DCM for frequency synthesis -- newbie question, PatC
      • Re: Xilinx DCM for frequency synthesis -- newbie question, Rob
      • Re: Xilinx DCM for frequency synthesis -- newbie question, mng
  • Re: Xilinx DCM for frequency synthesis -- newbie question, Bob Smith
    • Re: Xilinx DCM for frequency synthesis -- newbie question, John LeVieux
      • Re: Xilinx DCM for frequency synthesis -- newbie question, Bob Smith
      • Re: Xilinx DCM for frequency synthesis -- newbie question, JK
• Problem with PINs XC3S700A-4FG484, Fei Liu
  • Re: Problem with PINs XC3S700A-4FG484, jkljljklk
  • Re: Problem with PINs XC3S700A-4FG484, jkljljklk
    • Re: Problem with PINs XC3S700A-4FG484, Fei Liu
      • Re: Problem with PINs XC3S700A-4FG484, jkljljklk
      • Re: Problem with PINs XC3S700A-4FG484, Fei Liu
      • Re: Problem with PINs XC3S700A-4FG484, Dwayne Dilbeck
      • Re: Problem with PINs XC3S700A-4FG484, Fei Liu
• newbie seeking help to use xilinx spart-3a starter kit, Fei Liu
  • Re: newbie seeking help to use xilinx spart-3a starter kit, Frank Buss
    • Re: newbie seeking help to use xilinx spart-3a starter kit, Fei Liu
• Re: DDR SDRAM demo for Spartan-3E starter kit?, vankipuram
• Actel FPGA programming using libero 8.1 generated SVF files, Antti
  • Re: Actel FPGA programming using libero 8.1 generated SVF files, Antti
• Xilinx self-termination, Antti
  • Re: Xilinx self-termination, leevv
    • Re: Xilinx self-termination, Tim (one of many)
      • Re: Xilinx self-termination, lb . edc
• Software Defined Radio on Xilinx Virtex 4, auguste.chindji@xxxxxxxxxxxxxx
  • Re: Software Defined Radio on Xilinx Virtex 4, austin
  • Re: Software Defined Radio on Xilinx Virtex 4, Bart Fox
• How to use xilinx specific features from Modelsim Designer 6.3a VHDL, Stef
  • Re: How to use xilinx specific features from Modelsim Designer 6.3a VHDL, Mike Treseler
    • Re: How to use xilinx specific features from Modelsim Designer 6.3a VHDL, Stef
      • Re: How to use xilinx specific features from Modelsim Designer 6.3a VHDL, Mike Treseler
      • Re: How to use xilinx specific features from Modelsim Designer 6.3a VHDL, Stef
      • Re: How to use xilinx specific features from Modelsim Designer 6.3a VHDL, Mike Treseler
      • Re: How to use xilinx specific features from Modelsim Designer 6.3a VHDL, Stef
      • Re: How to use xilinx specific features from Modelsim Designer 6.3a VHDL, Mike Treseler
      • Re: How to use xilinx specific features from Modelsim Designer 6.3a VHDL, Stef
• Interview questions, Clemens Blank
  • Re: Interview questions, Clemens Blank
    • Re: Interview questions, Kevin Neilson
    • Re: Interview questions, jack.harvard@xxxxxxxxxxxxxx
      • Re: Interview questions, jack.harvard@xxxxxxxxxxxxxx
  • Re: Interview questions, John_H
    • Re: Interview questions, muthusnv
      • Re: Interview questions, Nir Dahan
  • Re: Interview questions, Jon Beniston
  • Re: Interview questions, Nico Coesel
    • Re: Interview questions, Symon
      • Re: Interview questions, Nico Coesel
      • Re: Interview questions, Philip Potter
      • Re: Interview questions, Symon
      • Re: Interview questions, MikeShepherd564
      • Re: Interview questions, Philip Potter
      • Re: Interview questions, checo
      • Re: Interview questions, Symon
      • Re: Interview questions, Philip Potter
      • Re: Interview questions, Mike Lewis
      • Re: Interview questions, Falk Brunner
  • Re: Interview questions, Gabor
• Software Defined Radio auf Xilinx Virtex 4, auguste . chindji
  • Re: Software Defined Radio auf Xilinx Virtex 4, info2
  • Re: Software Defined Radio auf Xilinx Virtex 4, austin
    • Re: Software Defined Radio auf Xilinx Virtex 4, Ray Andraka
  • Re: Software Defined Radio auf Xilinx Virtex 4, Peter Alfke
    • Re: Software Defined Radio auf Xilinx Virtex 4, MikeShepherd564
      • Re: Software Defined Radio auf Xilinx Virtex 4, Dwayne Dilbeck
    • Re: Software Defined Radio auf Xilinx Virtex 4, Kevin Neilson
      • Re: Software Defined Radio auf Xilinx Virtex 4, John_H
• which IOSTANDARD to use for IO-bank in Spartan-3, tmpstr
  • Re: which IOSTANDARD to use for IO-bank in Spartan-3, austin
    • Re: which IOSTANDARD to use for IO-bank in Spartan-3, tmpstr
• Reconfiguration (on the fly) using SPARTAN 3A, puneetjamrani
  • Re: Reconfiguration (on the fly) using SPARTAN 3A, austin
    • Re: Reconfiguration (on the fly) using SPARTAN 3A, Antti
      • Re: Reconfiguration (on the fly) using SPARTAN 3A, austin
      • Re: Reconfiguration (on the fly) using SPARTAN 3A, Antti
      • Re: Reconfiguration (on the fly) using SPARTAN 3A, austin
      • Re: Reconfiguration (on the fly) using SPARTAN 3A, puneetjamrani
      • Re: Reconfiguration (on the fly) using SPARTAN 3A, puneetjamrani
      • Re: Reconfiguration (on the fly) using SPARTAN 3A, John_H
      • Re: Reconfiguration (on the fly) using SPARTAN 3A, Antti
      • Re: Reconfiguration (on the fly) using SPARTAN 3A, vladitx
      • Re: Reconfiguration (on the fly) using SPARTAN 3A, austin
      • Re: Reconfiguration (on the fly) using SPARTAN 3A, Antti
      • Re: Reconfiguration (on the fly) using SPARTAN 3A, Andreas Ehliar
      • Re: Reconfiguration (on the fly) using SPARTAN 3A, Antti
      • Re: Reconfiguration (on the fly) using SPARTAN 3A, puneetjamrani
      • Re: ICAP in SPARTAN 3A, austin
      • Re: ICAP in SPARTAN 3A, Antti
      • Re: ICAP in SPARTAN 3A, austin
  • Re: Reconfiguration (on the fly) using SPARTAN 3A, Peter Alfke
    • Re: Reconfiguration (on the fly) using SPARTAN 3A, Antti
      • Re: Reconfiguration (on the fly) using SPARTAN 3A, Peter Alfke
      • Re: Reconfiguration (on the fly) using SPARTAN 3A, Antti
• System generator hardware co-simulation interface, cuga . smonster
• ADPCM IP Core, Goli
• Re: Random Number Generation in VHDL, Ray Andraka
  • <Possible follow-ups>
  • Re: Random Number Generation in VHDL, RCIngham
• V4FX: LVCMOS25 vs LVCMOS33 output buffer, MM
  • Re: LVCMOS25 vs LVCMOS33 output buffer, Symon
  • Re: V4FX: LVCMOS25 vs LVCMOS33 output buffer, austin
    • Re: V4FX: LVCMOS25 vs LVCMOS33 output buffer, MM
    • Re: V4FX: LVCMOS25 vs LVCMOS33 output buffer, BobW
      • Re: V4FX: LVCMOS25 vs LVCMOS33 output buffer, austin
      • Re: V4FX: LVCMOS25 vs LVCMOS33 output buffer, BobW
      • Re: V4FX: LVCMOS25 vs LVCMOS33 output buffer, austin
      • Re: V4FX: LVCMOS25 vs LVCMOS33 output buffer, austin
      • Re: V4FX: LVCMOS25 vs LVCMOS33 output buffer, austin
• Interrupt Handler page missing in from software platform settings in XPS 9.2i, radarman
  • Re: Interrupt Handler page missing in from software platform settings in XPS 9.2i, MadhuPankaj11
• Post PAR simulation is successful but still fails on the board, longbrmb
  • Re: Post PAR simulation is successful but still fails on the board, longbrmb
• From ASIC RTL to FPGA, what are the things I should take care of?, jasonL
  • Re: From ASIC RTL to FPGA, what are the things I should take care of?, info2
  • Re: From ASIC RTL to FPGA, what are the things I should take care of?, Dwayne Dilbeck
  • Re: From ASIC RTL to FPGA, what are the things I should take care of?, Ralf Hildebrandt
    • Re: From ASIC RTL to FPGA, what are the things I should take care of?, jasonL
• scanf problem in EDk 9.1i (Microbaze), MAx
  • Re: scanf problem in EDk 9.1i (Microbaze), Jan Pech
    • Re: scanf problem in EDk 9.1i (Microbaze), MAx
      • Re: scanf problem in EDk 9.1i (Microbaze), Jon Beniston
      • Re: scanf problem in EDk 9.1i (Microbaze), PFC
      • Re: scanf problem in EDk 9.1i (Microbaze), MAx
• Virtex5 BUFR min frequency, michel . talon
  • Re: Virtex5 BUFR min frequency, austin
• Which Linux Distro to use for Xilinx tools, Narendra Sisodiya
  • Re: Which Linux Distro to use for Xilinx tools, paragon . john
    • Re: Which Linux Distro to use for Xilinx tools, morphiend
      • Re: Which Linux Distro to use for Xilinx tools, Narendra Sisodiya
    • Re: Which Linux Distro to use for Xilinx tools, Jean-sébastien LEROY
      • Re: Which Linux Distro to use for Xilinx tools, John Williams
  • Re: Which Linux Distro to use for Xilinx tools, Sky465nm
    • Re: Which Linux Distro to use for Xilinx tools, Narendra Sisodiya
      • Re: Which Linux Distro to use for Xilinx tools, Sky465nm
      • Re: Which Linux Distro to use for Xilinx tools, Narendra Sisodiya
  • Re: Which Linux Distro to use for Xilinx tools, Tom Curran
  • Re: Which Linux Distro to use for Xilinx tools, John Williams
    • Re: Which Linux Distro to use for Xilinx tools, Narendra Sisodiya
  • Re: Which Linux Distro to use for Xilinx tools, Paul Boven
  • Re: Which Linux Distro to use for Xilinx tools, Eric Smith
• FPGA Programming solution, Alfreeeeed
  • Re: FPGA Programming solution, mh
  • Re: FPGA Programming solution, MikeShepherd564
    • Re: FPGA Programming solution, Alfreeeeed
      • Re: FPGA Programming solution, MikeShepherd564
      • Re: FPGA Programming solution, Alfreeeeed
      • Re: FPGA Programming solution, MikeShepherd564
    • Re: FPGA Programming solution, Tim (one of many)
      • Re: FPGA Programming solution, MikeShepherd564
      • Re: FPGA Programming solution, Alfreeeeed
      • Re: FPGA Programming solution, Bryan
      • Re: FPGA Programming solution, Jon Elson
      • Re: FPGA Programming solution, langwadt
      • Re: FPGA Programming solution, MikeShepherd564
      • Re: FPGA Programming solution, langwadt
      • Re: FPGA Programming solution, MikeShepherd564
      • Re: FPGA Programming solution, Alfreeeeed
      • Re: FPGA Programming solution, Jon Elson
      • Re: FPGA Programming solution, Jim Granville
      • Re: FPGA Programming solution, langwadt
      • Re: FPGA Programming solution, Jon Elson
      • Re: FPGA Programming solution, Antti
      • Re: FPGA Programming solution, MikeShepherd564
      • Re: FPGA Programming solution, Antti
      • Re: FPGA Programming solution, emeb
      • Re: FPGA Programming solution, emeb
      • Re: FPGA Programming solution, Antti
      • Re: FPGA Programming solution, MikeShepherd564
  • Re: FPGA Programming solution, comp.arch.fpga
  • Re: FPGA Programming solution, John_H
  • Re: FPGA Programming solution, Jon Elson
• MIG and Spartan3 for a 112 bit DQ bus (7chips x16), Dolphin
  • Re: MIG and Spartan3 for a 112 bit DQ bus (7chips x16), Nico Coesel
• Efficient division algorithm?, Nial Stewart
  • Re: Efficient division algorithm?, Uwe Bonnes
    • Re: Efficient division algorithm?, Nial Stewart
  • Re: Efficient division algorithm?, KJ
    • Re: Efficient division algorithm?, Nial Stewart
      • Re: Efficient division algorithm?, Mike Treseler
      • Re: Efficient division algorithm?, KJ
      • Re: Efficient division algorithm?, Mike Treseler
      • Re: Efficient division algorithm?, Alain
      • Re: Efficient division algorithm?, Tommy Thorn
      • Re: Efficient division algorithm?, KJ
  • Re: Efficient division algorithm?, Mike Treseler
    • Re: Efficient division algorithm?, KJ
      • Re: Efficient division algorithm?, Mike Treseler
  • Re: Efficient division algorithm?, Ray Andraka
    • Re: Efficient division algorithm?, Nial Stewart
      • Further Thoughts..., Nial Stewart
      • Re: Further Thoughts..., MikeShepherd564
      • Re: Further Thoughts..., Nial Stewart
  • Re: Efficient division algorithm?, Kevin Neilson
    • Re: Efficient division algorithm?, Ray Andraka
• Using Lattice ispLEVER with VHDL libraries, rickman
  • Re: Using Lattice ispLEVER with VHDL libraries, Colin Hankins
    • Re: Using Lattice ispLEVER with VHDL libraries, rickman
      • Re: Using Lattice ispLEVER with VHDL libraries, Colin Hankins
      • Re: Using Lattice ispLEVER with VHDL libraries, rickman
      • Re: Using Lattice ispLEVER with VHDL libraries, Jim Granville
      • Re: Using Lattice ispLEVER with VHDL libraries, Mike Treseler
      • Re: Using Lattice ispLEVER with VHDL libraries, rickman
      • Re: Using Lattice ispLEVER with VHDL libraries, Mike Treseler
      • Re: Using Lattice ispLEVER with VHDL libraries, troy . scott
      • Re: Using Lattice ispLEVER with VHDL libraries, Mike Treseler
      • Re: Using Lattice ispLEVER with VHDL libraries, rickman
• V4FX100 PowerPC PLB issues (and EDK 9.2), morphiend
  • Re: V4FX100 PowerPC PLB issues (and EDK 9.2), Antti
    • Re: V4FX100 PowerPC PLB issues (and EDK 9.2), morphiend
  • Re: V4FX100 PowerPC PLB issues (and EDK 9.2), Ben Jackson
• Define the primary clock with XST in VHDL, Julien Lochen
  • Re: Define the primary clock with XST in VHDL, KJ
  • Re: Define the primary clock with XST in VHDL, Mike Treseler
• MicroBlaze simulator, software ownership rights for SALE, Antti
  • Re: MicroBlaze simulator, software ownership rights for SALE, Dwayne Dilbeck
    • Re: MicroBlaze simulator, software ownership rights for SALE, Antti
      • Re: MicroBlaze simulator, software ownership rights for SALE, Jim Granville
• Interface on board ADC to Spartan 3E startkit, krunal
  • Re: Interface on board ADC to Spartan 3E startkit, Frank Buss
• Antti needs a job, Peter Alfke
  • Re: Antti needs a job, Jonathan Bromley
  • Re: Antti needs a job, BobW
    • Re: Antti needs a job, Peter Alfke
      • Re: Antti needs a job, Rob
      • Re: Antti needs a job, BobW
      • Re: Antti needs a job, Antti
      • Re: Antti needs a job, Thomas Reinemann
      • Re: Antti needs a job, Antti
  • Re: Antti needs a job, job
• Embedded in Nurnberg, Antti
• Video Over RF - using bluetooth and Xilinx Video Starter Kit, Narendra Sisodiya
  • Re: Video Over RF - using bluetooth and Xilinx Video Starter Kit, Jonathan Bromley
    • Re: Video Over RF - using bluetooth and Xilinx Video Starter Kit, Narendra Sisodiya
      • Re: Video Over RF - using bluetooth and Xilinx Video Starter Kit, Narendra Sisodiya
• Womens Plus Size Clothing Style Guide, astraumax
• Over utilization of FPGA resources, veriqiang
  • Re: Over utilization of FPGA resources, Frank Buss
    • Re: Over utilization of FPGA resources, Symon
  • Re: Over utilization of FPGA resources, Ben Jackson
• Synthesis-Place-Route benchmark for i386-32bit, fcdup8k
  • Re: Synthesis-Place-Route benchmark for i386-32bit, Daniel Koethe
  • Re: Synthesis-Place-Route benchmark for i386-32bit, Patrick Dubois
• Linux and the Digilent Basys ?, Bob Smith
  • Re: Linux and the Digilent Basys ?, Michael Trim
  • Re: Linux and the Digilent Basys ?, Andreas Ehliar
    • Re: Linux and the Digilent Basys ?, Bob Smith
      • Re: Linux and the Digilent Basys ?, sky465nm
• Ballpark PLB frequency, Steve
  • Re: Ballpark PLB frequency, Antti
    • Re: Ballpark PLB frequency, Steve
  • Re: Ballpark PLB frequency, Joseph Samson
  • Re: Ballpark PLB frequency, Jeff Cunningham
    • Re: Ballpark PLB frequency, Guru
      • Re: Ballpark PLB frequency, Jeff Cunningham
      • Re: Ballpark PLB frequency, Antti
      • Re: Ballpark PLB frequency, Jan Pech
      • Re: Ballpark PLB frequency, Antti
      • Re: Ballpark PLB frequency, Guru
      • Re: Ballpark PLB frequency, Jim Granville
      • Re: Ballpark PLB frequency, Guru
      • Re: Ballpark PLB frequency, Jeff Cunningham
      • Re: Ballpark PLB frequency, Antti
      • Re: Ballpark PLB frequency, Jeff Cunningham
      • Re: Ballpark PLB frequency, Andreas Ehliar
      • Re: Ballpark PLB frequency, Antti
  • Re: Ballpark PLB frequency, Ben Jackson
• Virtex 4 package layout, maxascent
  • Re: Virtex 4 package layout, austin
    • Re: Virtex 4 package layout, MikeShepherd564
      • Re: Virtex 4 package layout, Peter Alfke
      • Re: Virtex 4 package layout, MikeShepherd564
      • Re: Virtex 4 package layout, Symon
      • Re: Virtex 4 package layout, austin
      • Re: Virtex 4 package layout, maxascent
      • Re: Virtex 4 package layout, maxascent
  • Re: Virtex 4 package layout, austin
    • Re: Virtex 4 package layout, maxascent
      • Re: Virtex 4 package layout, austin
    • Re: Virtex 4 package layout, Gabor
• Spartan 3 configuration download error, Jürgen Böhm
  • Re: Spartan 3 configuration download error, Dwayne Dilbeck
    • Re: Spartan 3 configuration download error, Jürgen Böhm
      • Re: Spartan 3 configuration download error, Dwayne Dilbeck
      • Re: Spartan 3 configuration download error, Jürgen Böhm
  • Re: Spartan 3 configuration download error, Frank Buss
  • Re: Spartan 3 configuration download error, Peter Alfke
  • Re: Spartan 3 configuration download error, Brian Davis
• Reprogramming Proms,before the fpga boots from them (Avnet board,Xilinx Proms), giorgos . puiklis
• Microblaze 7.0 on V2pro?, Philip Potter
  • Re: Microblaze 7.0 on V2pro?, Alan Nishioka
  • Re: Microblaze 7.0 on V2pro?, austin
    • Re: Microblaze 7.0 on V2pro?, Philip Potter
      • Re: Microblaze 7.0 on V2pro?, austin
      • Re: Microblaze 7.0 on V2pro?, Markus
      • Re: Microblaze 7.0 on V2pro?, austin
  • Re: Microblaze 7.0 on V2pro?, austin
    • Re: Microblaze 7.0 on V2pro?, Philip Potter
• Rom Implementation in a CPLD, Marco T.
  • Re: Rom Implementation in a CPLD, Frank Buss
  • Re: Rom Implementation in a CPLD, Mike Harrison
  • Re: Rom Implementation in a CPLD, Jim Granville
• Cyclone flash configuration data, Frank Buss
  • Re: Cyclone flash configuration data, Mike Treseler
    • Re: Cyclone flash configuration data, MikeShepherd564
    • Re: Cyclone flash configuration data, Frank Buss
      • Re: Cyclone flash configuration data, Mike Treseler
• signal generation in VHDL on FPGA.... Check my code please, rossalbi
  • Re: signal generation in VHDL on FPGA.... Check my code please, Brian Drummond
  • Re: signal generation in VHDL on FPGA.... Check my code please, RCIngham
  • Re: signal generation in VHDL on FPGA.... Check my code please, PatC
  • Re: signal generation in VHDL on FPGA.... Check my code please, Rob
  • Re: signal generation in VHDL on FPGA.... Check my code please, Rehman
• i need fpga board with 10 Gig interface and pcie interface, rabbiaqamar
  • Re: i need fpga board with 10 Gig interface and pcie interface, Allan Herriman
    • Re: i need fpga board with 10 Gig interface and pcie interface, Symon
      • Re: i need fpga board with 10 Gig interface and pcie interface, Allan Herriman
    • Re: i need fpga board with 10 Gig interface and pcie interface, Ron Huizen
• i need ur help, rabbiaqamar
  • Re: i need ur help, muthusnv
• Erratic Behavior of Virtex 4 FPGA, Vijayan
  • Re: Erratic Behavior of Virtex 4 FPGA, mh
  • Re: Erratic Behavior of Virtex 4 FPGA, Grumps
  • Re: Erratic Behavior of Virtex 4 FPGA, Dunstan Power
• Virtex-4 input pad failures, RobJ
  • Re: Virtex-4 input pad failures, Symon
    • Re: Virtex-4 input pad failures, AugustoEinsfeldt
      • Re: Virtex-4 input pad failures, RobJ
    • Re: Virtex-4 input pad failures, RobJ
  • Re: Virtex-4 input pad failures, John_H
    • Re: Virtex-4 input pad failures, RobJ
  • Re: Virtex-4 input pad failures, Jon Elson
    • Re: Virtex-4 input pad failures, Jim Granville
• Virtex-5 User Guide "Lite", Peter Alfke
  • Re: Virtex-5 User Guide "Lite", bobster . thelobster
  • Re: Virtex-5 User Guide "Lite", Symon
• Is a FPGA the solution ?, L-C
  • Re: Is a FPGA the solution ?, RCIngham
    • Re: Is a FPGA the solution ?, Mike Harrison
  • Re: Is a FPGA the solution ?, Martin Thompson
  • Re: Is a FPGA the solution ?, Ray Andraka
• OT. Posting with Outlook Express?, Symon
• State machine outputs and tri-state, Grumps
  • Re: State machine outputs and tri-state, RCIngham
    • Re: State machine outputs and tri-state, Grumps
      • Re: State machine outputs and tri-state, bobster . thelobster
      • Re: State machine outputs and tri-state, bobster . thelobster
      • Re: State machine outputs and tri-state, Grumps
  • Re: State machine outputs and tri-state, backhus
    • Re: State machine outputs and tri-state, Grumps
      • Re: State machine outputs and tri-state, Grumps
• HELP on PLL and DCM, chestnut
  • Re: HELP on PLL and DCM, Symon
  • Re: HELP on PLL and DCM, austin
• Xilinx GTP_DUAL: wizard or code ?, tullio
  • Re: Xilinx GTP_DUAL: wizard or code ?, muthusnv
• When are FPGAs the right choice?, Mike Silva
  • Re: When are FPGAs the right choice?, chestnut
  • Re: When are FPGAs the right choice?, Symon
    • Re: When are FPGAs the right choice?, Mike Silva
      • Re: When are FPGAs the right choice?, Symon
  • Re: When are FPGAs the right choice?, Mike Harrison
    • Re: When are FPGAs the right choice?, Ray Andraka
  • Re: When are FPGAs the right choice?, Jim Granville
    • Re: When are FPGAs the right choice?, Mike Silva
  • Re: When are FPGAs the right choice?, Jon Elson
    • Re: When are FPGAs the right choice?, Gavin Scott
      • Re: When are FPGAs the right choice?, Sky465nm
    • Re: When are FPGAs the right choice?, Jim Granville
  • Re: When are FPGAs the right choice?, Sky465nm
  • Re: When are FPGAs the right choice?, Eric Smith
• setup time not met in Quartus, C-M, Chang
  • Re: setup time not met in Quartus, KJ
    • Re: setup time not met in Quartus, C-M, Chang
      • Re: setup time not met in Quartus, Mike Treseler
      • Re: setup time not met in Quartus, Peter Alfke
      • Re: setup time not met in Quartus, KJ
• floating point arithmetic in vhdl, Thorsten Kiefer
  • Re: floating point arithmetic in vhdl, Patrick Dubois
• mb-g++ compilation error with EDK 8.2.02i, Bathala
• Spartan 3A starter kit, anas_waris
  • Re: Spartan 3A starter kit, Eric Crabill
  • Re: Spartan 3A starter kit, Gavin Scott
  • Re: Spartan 3A starter kit, Thorsten Kiefer
• Newbie looking for guidance, everphilski@xxxxxxxxx
  • Re: Newbie looking for guidance, MikeShepherd564
  • Re: Newbie looking for guidance, MM
  • Re: Newbie looking for guidance, Gavin Scott
    • Re: Newbie looking for guidance, Martin Thompson
    • Re: Newbie looking for guidance, everphilski@xxxxxxxxx
      • Re: Newbie looking for guidance, Jonathan Bromley
      • Re: Newbie looking for guidance, Gavin Scott
  • Re: Newbie looking for guidance, Rob
    • Re: Newbie looking for guidance, everphilski@xxxxxxxxx
      • Re: Newbie looking for guidance, Jim Granville
• Redundant Ethernet connection, MM
  • Re: Redundant Ethernet connection, MM
• Virtex4FX over-voltage, morphiend
  • Re: Virtex4FX over-voltage, austin
  • Re: Virtex4FX over-voltage, Andy Botterill
    • Re: Virtex4FX over-voltage, John_H
      • Re: Virtex4FX over-voltage, morphiend
• XiRisc softcore processor, Jean-sébastien LEROY
  • Re: XiRisc softcore processor, Antti
    • Re: XiRisc softcore processor, Uncle Noah
      • Re: XiRisc softcore processor, Uncle Noah
      • Re: XiRisc softcore processor, Uncle Noah
      • Re: XiRisc softcore processor, Uncle Noah
      • Re: XiRisc softcore processor, Uncle Noah
      • Re: XiRisc softcore processor, Uncle Noah
      • Re: XiRisc softcore processor, Uncle Noah
  • Re: XiRisc softcore processor, Uncle Noah
    • Re: XiRisc softcore processor, Jean-sébastien LEROY
      • Re: XiRisc softcore processor, Uncle Noah
      • Re: XiRisc softcore processor, Jean-sébastien LEROY
• Does PC-FPGA communication requires a driver?, Vagant
  • Re: Does PC-FPGA communication requires a driver?, John_H
    • Re: Does PC-FPGA communication requires a driver?, Vagant
      • Re: Does PC-FPGA communication requires a driver?, Matthew Hicks
  • Re: Does PC-FPGA communication requires a driver?, deltabravosingh
  • Re: Does PC-FPGA communication requires a driver?, Ben Jackson
• '1' or '0' when I/O pin is pulled up, Nick
  • Re: '1' or '0' when I/O pin is pulled up, Jonathan Bromley
    • Re: '1' or '0' when I/O pin is pulled up, Nick
      • Re: '1' or '0' when I/O pin is pulled up, backhus
• Vitrex5 JTAG capture and debug, Rob
  • Re: Vitrex5 JTAG capture and debug, Rob
• Partial reconfiguration reference design?, Pasacco
• Reed solomon IP core, nezhate
  • Message not available
    • Re: Reed solomon IP core, nezhate
• how to implement this..., Dave
  • Re: how to implement this..., Symon
  • Re: how to implement this..., John_H
  • Re: how to implement this..., Jim Granville
  • Re: how to implement this..., backhus
    • Re: how to implement this..., comp.arch.fpga
      • Re: how to implement this..., backhus
      • Re: how to implement this..., Nir Dahan
      • Re: how to implement this..., John_H
      • Re: how to implement this..., Nir Dahan
  • Re: how to implement this..., glen herrmannsfeldt
• Xilinx ISE and XP home,possible?, blisca
  • Re: Xilinx ISE and XP home,possible?, John_H
    • Re: Xilinx ISE and XP home,possible?, blisca
• XC5VLX85-2FFG1153C, jon
  • Re: XC5VLX85-2FFG1153C, jon
• ModelSim versus Active-HDL....redux, paragon . john
  • Re: ModelSim versus Active-HDL....redux, Alfreeeeed
  • Re: ModelSim versus Active-HDL....redux, Duane Clark
    • Re: ModelSim versus Active-HDL....redux, nezhate
      • Re: ModelSim versus Active-HDL....redux, Matthew Hicks
      • Re: ModelSim versus Active-HDL....redux, RCIngham
      • Re: ModelSim versus Active-HDL....redux, Duane Clark
      • Re: ModelSim versus Active-HDL....redux, bobster . thelobster
      • Re: ModelSim versus Active-HDL....redux, Ray Andraka
      • Re: ModelSim versus Active-HDL....redux, Ray Andraka
  • Re: ModelSim versus Active-HDL....redux, Thomas Stanka
• Virtex5 DCM lower limit, michel . talon
  • Re: Virtex5 DCM lower limit, Antti
  • Re: Virtex5 DCM lower limit, Mike Treseler
  • Re: Virtex5 DCM lower limit, m
    • Re: Virtex5 DCM lower limit, michel . talon
  • Re: Virtex5 DCM lower limit, deltabravosingh
    • Re: Virtex5 DCM lower limit, beeraka@xxxxxxxxx
      • Re: Virtex5 DCM lower limit, michel . talon
      • Re: Virtex5 DCM lower limit, Mike Treseler
• FSL version compatability with Microblaze version, ratemonotonic
• Unsigned to signed vector., LilacSkin
  • Re: Unsigned to signed vector., Symon
  • Re: Unsigned to signed vector., comp.arch.fpga
    • Re: Unsigned to signed vector., LilacSkin
    • Re: Unsigned to signed vector., Jonathan Bromley
      • Re: Unsigned to signed vector., LilacSkin
      • Re: Unsigned to signed vector., Jonathan Bromley
      • Re: Unsigned to signed vector., LilacSkin
      • Re: Unsigned to signed vector., Jonathan Bromley
      • Re: Unsigned to signed vector., RCIngham
• Critical Path analysis, Clemens
  • Re: Critical Path analysis, Symon
  • Re: Critical Path analysis, deltabravosingh
• RC340E board to sell, Jean-sébastien LEROY
• FYI. Free Verilog cores from MIT., Symon
  • Re: FYI. Free Verilog cores from MIT., emeb
• Downloading codes to FPGA development Board, anas_waris
  • Re: Downloading codes to FPGA development Board, Sky465nm
  • Re: Downloading codes to FPGA development Board, hilo_pupu
  • Re: Downloading codes to FPGA development Board, pallavi
• loading unisim in modelsim problem while testin xilinx ipcore, kian . zarrin
  • Re: loading unisim in modelsim problem while testin xilinx ipcore, Mike Treseler
    • Re: loading unisim in modelsim problem while testin xilinx ipcore, bvkrock
  • Re: loading unisim in modelsim problem while testin xilinx ipcore, deltabravosingh
• ANN CPLD add-on module for Nintendo DS game console, Antti
  • Re: ANN CPLD add-on module for Nintendo DS game console, Symon
    • Re: ANN CPLD add-on module for Nintendo DS game console, Antti
• My first verilog/cpld project, DJ Delorie
  • Re: My first verilog/cpld project, Tommy Thorn
  • Re: My first verilog/cpld project, Arlet
    • Re: My first verilog/cpld project, DJ Delorie
  • Re: My first verilog/cpld project, MikeShepherd564
  • Re: My first verilog/cpld project, nospam
    • Re: My first verilog/cpld project, DJ Delorie
  • Re: My first verilog/cpld project, Jon Elson
    • Re: My first verilog/cpld project, John_H
    • Re: My first verilog/cpld project, Jim Granville
    • Re: My first verilog/cpld project, DJ Delorie
      • Re: My first verilog/cpld project, Dwayne Dilbeck
      • Re: My first verilog/cpld project, nospam
      • Re: My first verilog/cpld project, Dwayne Dilbeck
      • Re: My first verilog/cpld project, Jon Elson
      • Re: My first verilog/cpld project, Arlet Ottens
• multidimensional array, vijayant.rutgers@xxxxxxxxx
• Question to VHDL code fragment, Clemens
  • Re: Question to VHDL code fragment, KJ
• Timing Constraint not met, Clemens
  • Re: Timing Constraint not met, Mike Treseler
    • Re: Timing Constraint not met, morphiend
      • Re: Timing Constraint not met, chrisdekoh
      • Re: Timing Constraint not met, morphiend
      • Re: Timing Constraint not met, M. Hamed
• Problem in assignment of pins in PACE, hilo_pupu
• Strange "Style guide" requirements..., Nial Stewart
  • Re: Strange "Style guide" requirements..., Mike Treseler
  • Re: Strange "Style guide" requirements..., Jonathan Bromley
    • Re: Strange "Style guide" requirements..., Mike Treseler
      • Re: Strange "Style guide" requirements..., Mike Treseler
      • Re: Strange "Style guide" requirements..., Jonathan Bromley
      • Re: Strange "Style guide" requirements..., Nial Stewart
    • Re: Strange "Style guide" requirements..., Nial Stewart
      • Re: Strange "Style guide" requirements..., KJ
  • Re: Strange "Style guide" requirements..., Mark McDougall
    • Re: Strange "Style guide" requirements..., Mike Treseler
• Looking for a development board, Alfreeeeed
  • Re: Looking for a development board, Symon
    • Re: Looking for a development board, Alfreeeeed
      • Re: Looking for a development board, Symon
      • Re: Looking for a development board, Alfreeeeed
      • Re: Looking for a development board, Symon
      • Re: Looking for a development board, Michael Meeuwisse
  • Re: Looking for a development board, John Adair
    • Re: Looking for a development board, Alfreeeeed
• How to get Map Repoprt after System Generator postmap estimation, hilo_pupu
• impact bug or wrong interpretation of xsvf layout?, Michael Meeuwisse
  • Re: impact bug or wrong interpretation of xsvf layout?, mmihai
    • Re: impact bug or wrong interpretation of xsvf layout?, Michael Meeuwisse
      • Re: impact bug or wrong interpretation of xsvf layout?, Michael Meeuwisse
      • Re: impact bug or wrong interpretation of xsvf layout?, mmihai
      • Re: impact bug or wrong interpretation of xsvf layout?, Uwe Bonnes
      • Re: impact bug or wrong interpretation of xsvf layout?, Kolja Waschk
• Weired Distributed Memory behaviour, Gerry
  • Re: Weired Distributed Memory behaviour, Mike Treseler
  • Re: Weired Distributed Memory behaviour, Peter Alfke
    • Re: Weired Distributed Memory behaviour, Gerry
      • Re: Weired Distributed Memory behaviour, Symon
• I/O mode to use for USB ..?, Sky465nm
  • Re: I/O mode to use for USB ..?, Antti
    • Re: I/O mode to use for USB ..?, Sky465nm
      • Re: I/O mode to use for USB ..?, austin
      • Re: I/O mode to use for USB ..?, Sky465nm
      • Re: I/O mode to use for USB ..?, Mark McDougall
      • Re: I/O mode to use for USB ..?, Sky465nm
      • Re: I/O mode to use for USB ..?, Antti
• What does "Continuous Sample times are not allowed" mean in SysGen 9.1?, hilo_pupu
• Marking Flase paths for Timing Ignore + Virtex 2 Pro support, maverick
  • Re: Marking Flase paths for Timing Ignore + Virtex 2 Pro support, Symon
  • Re: Marking Flase paths for Timing Ignore + Virtex 2 Pro support, JuanC
  • Re: Marking Flase paths for Timing Ignore + Virtex 2 Pro support, Andreas Ehliar
• Prom alternatives for xilinx, taco
  • Re: Prom alternatives for xilinx, Gabor
    • Re: Prom alternatives for xilinx, taco
  • Re: Prom alternatives for xilinx, Antti
  • Re: Prom alternatives for xilinx, Walter
    • Re: Prom alternatives for xilinx, Antti
• ML410 and documentation on ALi M1535D+, GaLaKtIkUs(tm)
  • Re: ML410 and documentation on ALi M1535D+, Peter Ryser
    • Re: ML410 and documentation on ALi M1535D+, GaLaKtIkUs(tm)
• Shutdown parts of core logic on FPGA, H G
  • Re: Shutdown parts of core logic on FPGA, Falk Brunner
• Re: About 10-bit pixel datum from CMOS image sensor, Ray Andraka
• beleive, fbv999
  • Re: beleive, want . a . friendlier . world
    • Re: beleive, MikeShepherd564
      • Re: beleive, want.a.friendlier.world@xxxxxxxxx
  • Re: beleive, Eric Smith
    • Re: beleive, Ray Andraka
  • Re: beleive, Rob
• Re: FPGA's as DSP's, Ray Andraka
• Virtex5 not for SONET or SDH, hemulliken
  • Re: Virtex5 not for SONET or SDH, austin
  • Re: Virtex5 not for SONET or SDH, Goli
    • Virtex 5 and SONET/SDH, austin
• Partial Reconfiguration of Virtex-5: ISE and EAPR?, kyprianos
  • Re: Partial Reconfiguration of Virtex-5: ISE and EAPR?, austin
    • Re: Partial Reconfiguration of Virtex-5: ISE and EAPR?, shack19
      • Re: Partial Reconfiguration of Virtex-5: ISE and EAPR?, kyprianos
      • Re: Partial Reconfiguration of Virtex-5: ISE and EAPR?, austin
      • Re: Partial Reconfiguration of Virtex-5: ISE and EAPR?, shack19@xxxxxxxxx
      • Re: Partial Reconfiguration of Virtex-5: ISE and EAPR?, austin
      • Re: Partial Reconfiguration of Virtex-5: ISE and EAPR?, kyprianos
• Re: Actel Fusion FPGA, Rehman
• Single Top FPGA Tips, Tony Burch
  • Re: Single Top FPGA Tips, Falk Brunner
    • Re: Single Top FPGA Tips, Tony Burch
      • Re: Single Top FPGA Tips, John Retta
      • Re: Single Top FPGA Tips, KJ
      • Re: Single Top FPGA Tips, John Retta
      • Re: Single Top FPGA Tips, KJ
  • Re: Single Top FPGA Tips, want.a.friendlier.world@xxxxxxxxx
    • Re: Single Top FPGA Tips, Tony Burch
• Simple Memory Read problem, help appreciated, Gerry
  • Re: Simple Memory Read problem, help appreciated, Gerry
    • Re: Simple Memory Read problem, help appreciated, Gerry
      • Re: Simple Memory Read problem, help appreciated, KJ
      • Re: Simple Memory Read problem, help appreciated, Gerry
      • Re: Simple Memory Read problem, help appreciated, KJ
      • Re: Simple Memory Read problem, help appreciated, Peter Alfke
      • Re: Simple Memory Read problem, help appreciated, Gerry
      • Re: Simple Memory Read problem, help appreciated, John Retta
      • Re: Simple Memory Read problem, help appreciated, Gerry
      • Re: Simple Memory Read problem, help appreciated, Martin Thompson
      • Re: Simple Memory Read problem, help appreciated, Gerry
• Simulator error 607, Paul Boven
  • Re: Simulator error 607, Paul Boven
• 1-Wire and Dallas DS1WM in Spartan, Lars
  • Re: 1-Wire and Dallas DS1WM in Spartan, Frank Buss
  • Re: 1-Wire and Dallas DS1WM in Spartan, Ray Andraka
• OPB timer Microblaze, xenix
  • Re: OPB timer Microblaze, Alan Nishioka
    • Re: OPB timer Microblaze, xenix
• Re: BPSK CORDIC tracking, MM
• Problems with GDB in EDK 9.2, jcr_alr
  • Re: Problems with GDB in EDK 9.2, Markus
    • Re: Problems with GDB in EDK 9.2, jcr_alr
• ML505 with Petalinux, muthusnv
  • Re: ML505 with Petalinux, John Williams
    • Re: ML505 with Petalinux, muthusnv
• simulator options, FPGA
  • Re: simulator options, Mike Treseler
• Mobile Users: 4 thins you probably never knew your mobiles can do., Iqbal Sajid
• Sythesisable subset of VHDL, Gerry
  • Re: Sythesisable subset of VHDL, RCIngham
  • Re: Sythesisable subset of VHDL, David Spencer
• New leonardo spectrum version has license errors, robquigley
  • Re: New leonardo spectrum version has license errors, Mike Treseler
• GCLK overmapped, markmcmahon
  • Re: GCLK overmapped, Dwayne Dilbeck
• How to optimize my design area to fit?, hilo_pupu
  • Re: How to optimize my design area to fit?, Gabor
  • Re: How to optimize my design area to fit?, filter001
  • Re: How to optimize my design area to fit?, Dunstan Power
  • Re: How to optimize my design area to fit?, Chris Maryan
  • Re: How to optimize my design area to fit?, John Retta
  • Re: How to optimize my design area to fit?, Kevin Neilson
• MG Leonardo Synthesis Options, giorgos . puiklis
  • Re: MG Leonardo Synthesis Options, Mike Treseler
• A way to limit the data path delay, LilacSkin
  • Re: A way to limit the data path delay, Dunstan Power
    • Re: A way to limit the data path delay, LilacSkin
• Minimum Oscillator Frequency, Marco T.
  • Re: Minimum Oscillator Frequency, Gabor
    • Re: Minimum Oscillator Frequency, Marco T.
      • Re: Minimum Oscillator Frequency, AugustoEinsfeldt
      • Re: Minimum Oscillator Frequency, AugustoEinsfeldt
  • Re: Minimum Oscillator Frequency, Dunstan Power
    • Re: Minimum Oscillator Frequency, Symon
  • Re: Minimum Oscillator Frequency, PFC
• Possible CRC error on XC3S400 - now what?, Michael Meeuwisse
  • Re: Possible CRC error on XC3S400 - now what?, Sky465nm
    • Re: Possible CRC error on XC3S400 - now what?, Michael Meeuwisse
      • Re: Possible CRC error on XC3S400 - now what?, Gabor
      • Re: Possible CRC error on XC3S400 - now what?, Michael Meeuwisse
      • Re: Possible CRC error on XC3S400 - now what?, Sky465nm
      • Re: Possible CRC error on XC3S400 - now what?, Michael Meeuwisse
      • Re: Possible CRC error on XC3S400 - now what?, Gabor
      • Re: Possible CRC error on XC3S400 - now what?, Falk Brunner
      • Re: Possible CRC error on XC3S400 - now what?, Sky465nm
      • Re: Possible CRC error on XC3S400 - now what?, Michael Meeuwisse
      • Re: Possible CRC error on XC3S400 - now what?, Sky465nm
      • Re: Possible CRC error on XC3S400 - now what?, Brian Davis
      • Re: Possible CRC error on XC3S400 - now what?, Michael Meeuwisse
      • Re: Possible CRC error on XC3S400 - now what?, Sky465nm
      • Re: Possible CRC error on XC3S400 - now what?, Michael Meeuwisse
      • Re: Possible CRC error on XC3S400 - now what?, Sky465nm
      • Re: Possible CRC error on XC3S400 - now what?, AugustoEinsfeldt
      • Re: Possible CRC error on XC3S400 - now what?, Sky465nm
      • Re: Possible CRC error on XC3S400 - now what?, Thorsten Trenz
  • Re: Possible CRC error on XC3S400 - now what?, Thorsten Trenz
• 4-bit table look-up, Klaus Mayer
  • Re: 4-bit table look-up, Eric Smith
    • Re: 4-bit table look-up, Klaus Mayer
      • Re: 4-bit table look-up, Eric Smith
    • Re: 4-bit table look-up, Mark McDougall
      • Re: 4-bit table look-up, DJ Delorie
    • Re: 4-bit table look-up, Ed McGettigan
      • Re: 4-bit table look-up, Eric Smith
  • Re: 4-bit table look-up, Peter Alfke
• A video tutorial: The Xilinx FPGA Editor, eli . billauer
  • Re: A video tutorial: The Xilinx FPGA Editor, Daniel Koethe
    • Re: A video tutorial: The Xilinx FPGA Editor, eli . billauer
  • Re: A video tutorial: The Xilinx FPGA Editor, Dwayne Dilbeck
• Re: Scaling data, RCIngham
  • Re: Scaling data, Anuja
• forcing "Unused IOB Pin -> " from .ucf, job
• Re: microblaze question, taco
  • <Possible follow-ups>
  • Re: microblaze question, mmihai
• OFFSET In and hold time, LilacSkin
  • Re: OFFSET In and hold time, John McCaskill
• Server configuration for Virtex5, Goli
  • Re: Server configuration for Virtex5, Rob
    • Re: Server configuration for Virtex5, Sky465nm
      • Re: Server configuration for Virtex5, Goli
• Call For Papers: FPL 2008, David Thomas
• Bitstream verification through readback, maverick
  • Re: Bitstream verification through readback, austin
  • Re: Bitstream verification through readback, Jeff Cunningham
  • Re: Bitstream verification through readback, Rob
  • Re: Bitstream verification through readback, Dunstan Power
  • Re: Bitstream verification through readback, Sky465nm
• Starting problems with ISE 9.2.04i (WebPack+ServicePack)...unable to set Spartan-3E as target, pallavi
  • Re: Starting problems with ISE 9.2.04i (WebPack+ServicePack)...unable to set Spartan-3E as target, Arlet Ottens
    • Re: Starting problems with ISE 9.2.04i (WebPack+ServicePack)...unable to set Spartan-3E as target, Dwayne Dilbeck
      • Re: Starting problems with ISE 9.2.04i (WebPack+ServicePack)...unable to set Spartan-3E as target, pallavi
• Re: My first Flash FPGA, Antti
  • Re: My first Flash FPGA, Jim Granville
  • <Possible follow-ups>
  • Re: My first Flash FPGA, Antti
• Internal signal names in ModelSim, Xin Xiao
  • Re: Internal signal names in ModelSim, KJ
  • Re: Internal signal names in ModelSim, John Retta
  • Re: Internal signal names in ModelSim, mk
    • Re: Internal signal names in ModelSim, Analog_Guy
• Loading from Compact Flash on ML310..., Xesium
  • Re: Loading from Compact Flash on ML310..., Ed McGettigan
    • Re: Loading from Compact Flash on ML310..., Xesium
      • Re: Loading from Compact Flash on ML310..., Ed McGettigan
• spartan3a support DVI ?, huangjie
  • Re: spartan3a support DVI ?, austin
    • Re: spartan3a support DVI ?, huangjie
      • Re: spartan3a support DVI ?, Antti
• Re: Fixedpoint Multiply/Accumulate in DSP48, comp.arch.fpga
• Re: Design security for pre-Virtex2 parts ?, Marlboro
  • <Possible follow-ups>
  • Re: Design security for pre-Virtex2 parts ?, Kris Vorwerk
• Re: Low Pin Count (LPC) bus code available?, TC
  • Re: Low Pin Count (LPC) bus code available?, johnp
• Keeping Xilinx tool from Optimizing out Debugging signals, M. Hamed
  • Re: Keeping Xilinx tool from Optimizing out Debugging signals, austin
    • Re: Keeping Xilinx tool from Optimizing out Debugging signals, M. Hamed
• Xilinx timming analysis, LilacSkin
  • Re: Xilinx timming analysis, austin
  • Re: Xilinx timming analysis, Symon
• Re: Why does a 36 x 36 Multiplier in a Xilinx Spartan 3E require 9 multipliers?, comp.arch.fpga
• Gemac on ML402, Josue P. J. de Freitas
• Re: Xilinx BSCAN primitives proper use, mh
  • Re: Xilinx BSCAN primitives proper use, emeb
    • Re: Xilinx BSCAN primitives proper use, mk
      • Re: Xilinx BSCAN primitives proper use, mh
      • Re: Xilinx BSCAN primitives proper use, posedge52
      • Re: Xilinx BSCAN primitives proper use, mh
  • <Possible follow-ups>
  • Re: Xilinx BSCAN primitives proper use, kjc
• Re: I need a SDRAM controller, PFC
• Re: question about fsl and microblaze, Göran Bilski
  • Re: question about fsl and microblaze, u_stadler@xxxxxxxx
    • Re: question about fsl and microblaze, Göran Bilski
• Re: FPGA in Telecommunications, Thomas Stanka
• Why use small resistor for Vcco voltage regulator, jasonL
  • Re: Why use small resistor for Vcco voltage regulator, Jim Granville
  • Re: Why use small resistor for Vcco voltage regulator, Symon
    • Re: Why use small resistor for Vcco voltage regulator, Bas Laarhoven
      • Re: Why use small resistor for Vcco voltage regulator, Symon
      • Re: Why use small resistor for Vcco voltage regulator, Jim Granville
      • Re: Why use small resistor for Vcco voltage regulator, Eric Crabill
      • Re: Why use small resistor for Vcco voltage regulator, Falk Brunner
      • Re: Why use small resistor for Vcco voltage regulator, Jim Granville
      • Re: Why use small resistor for Vcco voltage regulator, jasonL
      • Re: Why use small resistor for Vcco voltage regulator, Jim Granville
  • Re: Why use small resistor for Vcco voltage regulator, John Adair
• Loading the design from Compact Flash..., Xesium
  • Re: Loading the design from Compact Flash..., David
    • Re: Loading the design from Compact Flash..., Xesium
      • Re: Loading the design from Compact Flash..., David
      • Re: Loading the design from Compact Flash..., Xesium
      • Re: Loading the design from Compact Flash..., D . J . Mulligan
      • Re: Loading the design from Compact Flash..., Xesium

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