Re: Basic FPGA question about Reset

On Wed, 16 Jan 2008 10:22:39 -0800, austin <austin@xxxxxxxxxx> wrote:

G.

How one starts the configuration process is a different problem that how
the device after configuration, starts up.

The first problem is often caused by people "not trusting" the internal
Power On Reset circuits in the FPGA: bad. We spend an immense amount
of time making sure the POR circuits work under all sequences, and all
ramps from 2us to 50ms. Mess with this, and then you have to do all the
engineering for three power supplies to make it work at least as well as
we already did. Not a smart move. Why would anyone want to re-invent
this wheel?

There are a few reasons why you would want to re-invent that wheel in
a practical product:

1. "all ramps from 2us to 50ms"
It may be impossible to guarantee the 50ms end of that, particularly
in mains powered circuits. If there is a slow brownout, an external
reset generator with accurate thresholds *will* result in a more
reliable design.

2. I find that my designs rarely contain just an FPGA. I have a
whole host (sorry about the pun) of items on the board that need to be
reset at the same time.

2b. Sometimes (particularly when I have a host processor on the board
that configures the FPGA) I want to have different parts of the board
reset based on different criteria.

3. I also have extra voltage rails that need to be monitored, and
these rails aren't connected to the FPGA. An external reset generator
is required to monitor those rails.


If FPGAs had an on-die reset generator that
- was guaranteed to work for all ramp rates
- was guaranteed to work for non-monotonic ramps
- could monitor 3-4 additional voltages
- had a guaranteed 2% voltage tolerance or better
- had threshold voltages I can set (or determine by resistor ratios)
- had a dedicated reset output to drive other parts of the board,

I would use it. Until then, I will use cheap, reliable, external
reset generator devices.


Regards,
Allan


After the product has loaded the configuration, and has completed the
start-up sequence, then everything is in a known state, so a reset isn't
even required (it is implicit in the starting values you placed in the
registers in your VHDL or verilog code, and was part of the loaded
bitstream).

If at some time later, you want to return to a 'known good state', which
we will call "reset" for no better reason than it describes the action
you want to take, then the applications note (or the old Tech X) details
all kinds of ways to do this, that work.

Austin
.

Relevant Pages

  • Re: Spartan 3 chips in power up
    ... Spartan 3 is held in reset until all three power supplies are fully up. ... I get a lot of grief from the FPGA firmware designers on every little ... FPGA power is fully up and also operating the DSP while the FPGA power ...
    (comp.arch.fpga)
  • Re: Mixed clocked/combinatorial coding styles
    ... But this requires the global set reset signal. ... That is how the FFs ... values for the signals. ... FPGA are quite slow. ...
    (comp.lang.vhdl)
  • Re: Register with a default Value
    ... conditions that cannot be repeated when you externally reset the ... in the FPGA, leaving it in its unprogrammed state? ... glitches, or just bad design. ... recovered clock and data to a brand X series 4000 FPGA. ...
    (comp.lang.vhdl)
  • Re: Need for reset in FPGAs
    ... usually a reset signal is applied to put the FFs of an FPGA into a known ... Whether or not you need a reset depends on your design and the ... that are asynchronous to the FSM clock. ...
    (comp.arch.fpga)
  • Re: Need for reset in FPGAs
    ... usually a reset signal is applied to put the FFs of an FPGA into a known ... The FFs always come up in a guaranteed way after power-up - the ... bitstream you feed into the FPGA defines their power-up state. ...
    (comp.arch.fpga)