Re: converting verilog to vhdl

On Dec 7, 10:15 am, Andy <jonesa...@xxxxxxxxxxx> wrote:
On Dec 7, 8:14 am, Anuja <thakkar.an...@xxxxxxxxx> wrote:





On Dec 7, 4:02 am, "RCIngham" <robert.ing...@xxxxxxxxx> wrote:

On Dec 6, 9:43 am, "RCIngham" <robert.ing...@xxxxxxxxx> wrote:
On Dec 4, 5:56 pm, Eric Smith <e...@xxxxxxxxxxxx> wrote:
Anuja wrote:
assign Q = (rst==0)?Q_int:1'do;

How do i convert this to vhdl? I have to use a concurrent
statement
as

Q <= Q_int when rst = '0' else '0';

Hi,

I am having simulation problems with my code. I am trying to convert
Verilog code to VHDL. I can compile correctly. When i simulate the
following code in VHDL, value of Q_int is stuck at "00". It does not
change at all. Please let me know what the problem could be.

Remove the line:

Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else "00";

after the BEGIN of the architecture.- Hide quoted text -

- Show quoted text -

How do i implement the logic assign Q = (rst == 0)? Q_int : 2'd0;

if i remove Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else
"00";

Sorry, my bad. I read your code too quickly, and thought you were
assigning to Q in the clocked precess as well.

Try:
Q(1 downto 0) <= Q_int(1 downto 0) when rst = '0' else "00";
Or better:
Q(1 downto 0) <= "00" when rst = '1' else Q_int(1 downto 0);- Hide quoted text -

- Show quoted text -

neither one works. I am still having the same problem

I'm not sure where you got the code, but it looks like it is a flop
with a synchronous reset and enable, and then anding the output with
reset after the register.

I would convert it as follows to a standard asynchronous reset
circuit. The only difference in behavior would be if rst is high for
less than a clock cycle, but not while the clock is actually rising
(in which case the original circuit output would be 0 while rst, but
return to whatever q_int was afterwards, whereas the new circuit will
stay at 0 until something is clocked into q).

process (clk, rst) is
begin
if rst = '1' then
q <= (others => '0');
elsif rising_edge(clk) and (en = '1') then
q <= d;
end if;
end process;

Hints: you don't need to write "(1 downto 0)" when that is the entire
range of the array/vector. In a clocked process, you also don't need
to reassign q (or q_int) to itself when it needs to remain the same.

and get rid of that concurrent statement (it is handled now by the
async reset)

Andy- Hide quoted text -

- Show quoted text -

I tried the solution you gave me. I am still having the same problem,
Q or Q_int is still "00" at all time
.

Relevant Pages

  • Re: converting verilog to vhdl
    ... Verilog code to VHDL. ... reset after the register. ... The only difference in behavior would be if rst is high for ... (in which case the original circuit output would be 0 while rst, ...
    (comp.arch.fpga)
  • Re: Simple One Shot circuit needed
    ... circuit will stay off until it is manually reset. ... the switch is opened the circuit is activated and the pulse will be created. ... You can do something like shown below but I would recommend adding a POR IC with open drain output connected to RST node shown with '*'. ...
    (sci.electronics.design)
  • Re: converting verilog to vhdl
    ... Verilog code to VHDL. ... reset after the register. ... The only difference in behavior would be if rst is high for ... (in which case the original circuit output would be 0 while rst, ...
    (comp.arch.fpga)
  • Re: converting verilog to vhdl
    ... Verilog code to VHDL. ... reset after the register. ... The only difference in behavior would be if rst is high for ... less than a clock cycle, but not while the clock is actually rising ...
    (comp.arch.fpga)
  • Timer
    ... I need to design a timer in vhdl from 0 min:00 sec to 9min:59 sec. the ... circuit must have a start, stop and reset buttons. ...
    (comp.lang.vhdl)