Re: Traffic Light with counter
- From: "John Adair" <removethisthenleavejea@xxxxxxxxxxxxxxxxxxxxxxxxxxxx>
- Date: Mon, 3 Dec 2007 14:35:34 -0000
Start by defining a state machine that has all the states you need and
outline the transitions you need qualified with counter. An example (NOT
SYNTAX CHECKED) of 4 states below.
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TRAFFIC IS
PORT( CLOCK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
OP1 : OUT STD_LOGIC;
OP2 : OUT STD_LOGIC);
END TRAFFIC;
ARCHITECTURE A0 OF TRAFFIC IS
SIGNAL COUNTER : INTEGER RANGE 0 TO 10000000;
TYPE SM_TRAFFIC_TYPE IS( SM_TRAFFIC_IDLE ,
SM_TRAFFIC_OP1_ON ,
SM_TRAFFIC_OP2_ON ,
SM_TRAFFIC_OP1_OP2_ON );
SIGNAL SM_TRAFFIC : SM_TRAFFIC_TYPE;
BEGIN
TR1 : PROCESS(RESET,CLOCK)
BEGIN
IF (RESET = '1') THEN
SM_TRAFFIC <= SM_TRAFFIC_IDLE;
COUNTER <= 1000;
OP1 <= '0';
OP2 <= '0';
ELSIF (CLOCK'EVENT AND CLOCK='1') THEN
CASE SM_TRAFFIC IS
WHEN SM_TRAFFIC_IDLE =>
SM_TRAFFIC <= SM_TRAFFIC_OP1_ON;
COUNTER <= 1000;
OP1 <= '1';
OP2 <= '0';
--STAY GERE 1000 CLOCKS
WHEN SM_TRAFFIC_OP1_ON =>
IF (COUNTER = 0) THEN
SM_TRAFFIC <= SM_TRAFFIC_OP2_ON;
COUNTER <= 5000000;
OP1 <= '0';
OP2 <= '1';
ELSE
SM_TRAFFIC <= SM_TRAFFIC_OP1_ON;
COUNTER <= COUNTER - 1;
OP1 <= '1';
OP2 <= '0';
END IF;
--STAY HERE 5000000 CLOCKS
WHEN SM_TRAFFIC_OP2_ON =>
IF (COUNTER = 0) THEN
SM_TRAFFIC <= SM_TRAFFIC_OP1_OP2_ON;
COUNTER <= 4000000;
OP1 <= '1';
OP2 <= '1';
ELSE
SM_TRAFFIC <= SM_TRAFFIC_OP2_ON;
COUNTER <= COUNTER - 1;
OP1 <= '0';
OP2 <= '1';
END IF;
--SM_TRAFFIC_OP1_OP2_ON
--STAY HERE 4000000 CLOCKS
WHEN OTHERS =>
IF (COUNTER = 0) THEN
SM_TRAFFIC <= SM_TRAFFIC_OP1_ON;
COUNTER <= 1000;
OP1 <= '1';
OP2 <= '0';
ELSE
SM_TRAFFIC <= SM_TRAFFIC_OP2_ON;
COUNTER <= COUNTER - 1;
OP1 <= '0';
OP2 <= '0';
END IF;
END CASE;
END IF;
END PROCESS TR1;
END A0 ;
John Adair
Enterpoint Ltd.
Home of Drigmorn1. The hobby FPGA Development Board.
"tang" <tarangpatel2electric@xxxxxxxxx> wrote in message
news:9aa0272a-6372-4cf9-a429-cf85a9b584bb@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
On Dec 1, 1:59 am, John Adair <g...@xxxxxxxxxxxxxxxx> wrote:
There are a large number of ways you could do this. Personally I'm not
a get fan of next state, current state, style you use but it does have
it's followers.
Staying with what you have I would check the asychronous
(combinatorial) processes have complete sensativity lists. Your
clocked processes I would make sure all statements lie with the clock
and reset statements.
Personally I would have a counter that reloaded with values linked to
the transitions of the state machine and taking a count value relevant
to the state being entered. The counter then counts down to zero and
then the next state transition. If you make your counter integer type
you don't need extra numerical type libraries.
John Adair
Enterpoint Ltd. - Home of Craignells The obsolete DIL solution.
On 30 Nov, 22:12, tang <tarangpatel2elect...@xxxxxxxxx> wrote:
hey guys i hope u can help me out... i want to design a simple traffic
light controller according to the 4 states shown in the code below. my
only problem is that my signal state_reg is not changing form one
state to another. this is because the counter i included in the the
code as a process is not working. green to yellow time wait is 30 sec
and yellow to red is 5 sec. my clock period will be 5 sec. so can
anyone help me out
------------------------------------------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity TLC is
port(
clk,reset, sa, sb:in std_logic;
Ga, Ya, Ra, Gb, Yb, Rb:out std_logic
);
end TLC;
architecture Behavioral of TLC is
type state_type is (a, b, c, d);
signal state_reg, state_next: state_type;
signal Pre_Q, Q: std_logic_vector(3 downto 0);
signal count, clear: std_logic;
begin
-- behavior describe the counter
process(clk, count, clear)
begin
if (clear = '0') then
Pre_Q <= Pre_Q - Pre_Q;
elsif (clk='1' and clk'event) then
if (count = '1') then
Pre_Q <= Pre_Q + 1;
end if;
end if;
Q <= Pre_Q;
end process;
-- state register
process(clk,reset)
begin
if(reset='0') then
state_reg <= a;
elsif (clk'event and clk='1') then
state_reg <= state_next;
end if;
end process;
-- next state logic
process(state_reg,Q,sa,sb)
begin
case state_reg is
when a =>
if(sa = '1' and sb = '0')then
state_next <= a;
elsif (sa = '0' and sb = '1') then
count <= '1';
if(Q = "0110") then
state_next <= b;
end if;
end if;
when b =>
if(Q = "0111") then
state_next <= c;
count <= '0';
elsif(sa = '1') then
state_next <= b;
end if;
when c =>
if(sa = '0' and sb = '1') then
state_next <= c;
elsif (sa = '1' and sb ='0') then
clear <= '0';
count <= '1';
if(Q = "0110") then
state_next <= d;
end if;
end if;
when d =>
if(Q = "0111") then
state_next <= a;
count <= '0';
elsif(sb = '1') then
state_next <= d;
end if;
end case;
end process;
process (state_reg)
begin
Ga <= '1'; Ya <= '0'; Ra <= '0';
Gb <= '0'; Yb <= '0'; Rb <= '1';
case state_reg is
when a =>
when b =>
Ga <= '0';
Ya <= '1';
when c =>
Ya <= '0';
Ra <= '1';
Gb <= '1';
when d =>
Gb <= '0';
Yb <= '1';
end case;
end process;
end Behavioral;
----------------------------------------------------------------------------------------------------------------------------------------------------------
Thanx for the solution. I was also thinking about making counter
integer. Can you please elaborate on that? will it be like adding for
loop till count reach to desired value and then perform the
transition?
thanx again
.
- References:
- Re: Traffic Light with counter
- From: John Adair
- Re: Traffic Light with counter
- From: tang
- Re: Traffic Light with counter
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