comp.arch.fpga

• Date Index

• ERROR iMPACT 477 - The bsdl for the device 'UNKNOWN' is out of date, Mike Gragger
• keep_hierarchy attribute equivalent for Lattice/Synplicity?, theosib@xxxxxxxxx
• Questions about Timing closure Floorplan and individual timing constraints, commone
• Net hierarchy with Xilinx 9.1, Louis Dupont
• Xilinx EDK simulation, cwoodring
  • Re: Xilinx EDK simulation, Daniel Koethe
• What to look for when synthesising verilog code originally written for ASIC to FPGA?, wei . wang . cantab
  • Re: What to look for when synthesising verilog code originally written for ASIC to FPGA?, emeb
• Drigmorn1 More Info, John Adair
• DDS generator with interpolated samples for Spartan3E development board, Frank Buss
  • Re: DDS generator with interpolated samples for Spartan3E development board, Mike Treseler
  • Re: DDS generator with interpolated samples for Spartan3E development board, emeb
  • Re: DDS generator with interpolated samples for Spartan3E development board, KJ
  • Re: DDS generator with interpolated samples for Spartan3E development board, Allan Herriman
    • Re: DDS generator with interpolated samples for Spartan3E development board, John Larkin
      • Re: DDS generator with interpolated samples for Spartan3E development board, Frank Buss
      • Re: DDS generator with interpolated samples for Spartan3E development board, John Larkin
• problem interfacing AD9510 via serial controller, naliali
  • Re: problem interfacing AD9510 via serial controller, rickman
• Which FPGA and memory to use? The eternal X vs. A question., Alex Freed
  • Re: Which FPGA and memory to use? The eternal X vs. A question., Marc Randolph
    • Re: Which FPGA and memory to use? The eternal X vs. A question., Marc Randolph
      • Re: Which FPGA and memory to use? The eternal X vs. A question., Alex Freed
      • Re: Which FPGA and memory to use? The eternal X vs. A question., Marc Randolph
      • Re: Which FPGA and memory to use? The eternal X vs. A question., Alex Freed
  • Re: Which FPGA and memory to use? The eternal X vs. A question., Kris Vorwerk
  • Re: Which FPGA and memory to use? The eternal X vs. A question., Nico Coesel
    • Re: Which FPGA and memory to use? The eternal X vs. A question., Subroto Datta
      • Re: Which FPGA and memory to use? The eternal X vs. A question., Alex Freed
    • Re: Which FPGA and memory to use? The eternal X vs. A question., KJ
      • Re: Which FPGA and memory to use? The eternal X vs. A question., Nico Coesel
  • Re: Which FPGA and memory to use? The eternal X vs. A question., Nico Coesel
    • Re: Which FPGA and memory to use? The eternal X vs. A question., Alex Freed
      • Re: Which FPGA and memory to use? The eternal X vs. A question., rickman
      • Re: Which FPGA and memory to use? The eternal X vs. A question., Nico Coesel
• the FPGA gate way, guochenglv
• Pin assignment with Quartus II for PCB placement, steve_blah
  • Re: Pin assignment with Quartus II for PCB placement, KJ
    • Re: Pin assignment with Quartus II for PCB placement, steve_blah
  • Re: Pin assignment with Quartus II for PCB placement, Mike Treseler
    • Re: Pin assignment with Quartus II for PCB placement, steve_blah
  • Re: Pin assignment with Quartus II for PCB placement, Subroto Datta
    • Re: Pin assignment with Quartus II for PCB placement, steve_blah
• virtex II pro - own core on plb with 2 interrupts, SvenA
  • Re: virtex II pro - own core on plb with 2 interrupts, Matthew Hicks
• selecting FPGA, bish
  • Re: selecting FPGA, John Adair
  • Re: selecting FPGA, Kris Vorwerk
• usb cable driver, Andre van der Avoird
  • Re: usb cable driver, John_H
    • Re: usb cable driver, Andre van der Avoird
      • Re: usb cable driver, John_H
      • Re: usb cable driver, Andre van der Avoird
      • Re: usb cable driver, Matthew Hicks
      • Re: usb cable driver, google
• Help! I want give MGTREFCLK LVDS clock to GTP_DUAL (FPGA-Virtex5), axalay
  • Re: Help! I want give MGTREFCLK LVDS clock to GTP_DUAL (FPGA-Virtex5), axalay
  • Re: Help! I want give MGTREFCLK LVDS clock to GTP_DUAL (FPGA-Virtex5), Ed McGettigan
    • Re: Help! I want give MGTREFCLK LVDS clock to GTP_DUAL (FPGA-Virtex5), Sean Durkin
    • Re: Help! I want give MGTREFCLK LVDS clock to GTP_DUAL (FPGA-Virtex5), axalay
• SDRAM and S3E - is the example broken?, Alex Freed
  • Re: SDRAM and S3E - is the example broken?, jaroslav . sykora
• For God's sake !! It did not work at all !!!, matadouros . home
  • Re: For God's sake !! It did not work at all !!!, Kevin Neilson
    • Re: For God's sake !! It did not work at all !!!, Symon
  • Re: For God's sake !! It did not work at all !!!, John_H
• Seeking help on xilkernel, 思考 (斌)
• student requiring assistance :), truongt1024
  • Re: student requiring assistance :), Guenter Dannoritzer
  • Re: student requiring assistance :), ghelbig
  • Re: student requiring assistance :), BobW
  • Re: student requiring assistance :), Aiken
• Using FSL with Interrupts, ratemonotonic
  • Re: Using FSL with Interrupts, John Williams
    • Re: Using FSL with Interrupts, ratemonotonic
• Synplify .sdc file, wei . wang . cantab
  • Re: Synplify .sdc file, kkoorndyk
• Spartan-3E starter kit, USB Jtag, posedge52
• How can I get data from Altera Triple Speed Ethernet (TSE) MAC through Avalon bus?, Yui
  • Re: How can I get data from Altera Triple Speed Ethernet (TSE) MAC through Avalon bus?, ghelbig
    • Re: How can I get data from Altera Triple Speed Ethernet (TSE) MAC through Avalon bus?, Tommy Thorn
    • Re: How can I get data from Altera Triple Speed Ethernet (TSE) MAC through Avalon bus?, KJ
      • Re: How can I get data from Altera Triple Speed Ethernet (TSE) MAC through Avalon bus?, Aiken
      • Re: How can I get data from Altera Triple Speed Ethernet (TSE) MAC through Avalon bus?, KJ
      • Re: How can I get data from Altera Triple Speed Ethernet (TSE) MAC through Avalon bus?, Tommy Thorn
      • Re: How can I get data from Altera Triple Speed Ethernet (TSE) MAC through Avalon bus?, Tommy Thorn
      • Re: How can I get data from Altera Triple Speed Ethernet (TSE) MAC through Avalon bus?, KJ
• reconfigurable, modular design and clock signals - Question, l.s.rockfan@xxxxxx
  • Re: reconfigurable, modular design and clock signals - Question, austin
    • Re: reconfigurable, modular design and clock signals - Question, L. Schreiber
      • Re: reconfigurable, modular design and clock signals - Question, austin
      • Re: reconfigurable, modular design and clock signals - Question, L. Schreiber
• ideas - gatgets de arte, diseño, arquitectura y tecnología, marc
• Drigmorn1 - The Cheapest FPGA Development Board???, John Adair
  • Re: Drigmorn1 - The Cheapest FPGA Development Board???, posedge52
    • Re: Drigmorn1 - The Cheapest FPGA Development Board???, HT-Lab
      • Re: Drigmorn1 - The Cheapest FPGA Development Board???, Mike Harrison
    • Re: Drigmorn1 - The Cheapest FPGA Development Board???, John Adair
      • Message not available
      • Re: Drigmorn1 - The Cheapest FPGA Development Board???, John Adair
  • Re: Drigmorn1 - The Cheapest FPGA Development Board???, Mike Harrison
    • Re: Drigmorn1 - The Cheapest FPGA Development Board???, John Adair
• why do i see negative clock hold time, guy
  • Re: why do i see negative clock hold time, David Spencer
  • Re: why do i see negative clock hold time, KJ
• Mixed language design, MikeShepherd564
  • Re: Mixed language design, John McCaskill
    • Re: Mixed language design, MikeShepherd564
      • Re: Mixed language design, Gabor
      • Re: Mixed language design, Mike Treseler
      • Re: Mixed language design, John McCaskill
  • Re: Mixed language design, Ray Andraka
    • Re: Mixed language design, glen herrmannsfeldt
  • Re: Mixed language design, MikeShepherd564
• Re: Low cost FPGA w/serdes, dowers . irl
  • Re: Low cost FPGA w/serdes, MikeShepherd564
    • Re: Low cost FPGA w/serdes, dowers . irl
• can't install Centos 5.1 x86_64 and Xilinx ISE 9.2 evaluation, Helpme
  • Re: can't install Centos 5.1 x86_64 and Xilinx ISE 9.2 evaluation, Jan Pech
  • Re: can't install Centos 5.1 x86_64 and Xilinx ISE 9.2 evaluation, General Schvantzkopf
• Need help with Altera .pof format!, larstore
• "simultaneously switching output", wojjed
  • Re: "simultaneously switching output", Symon
    • Re: "simultaneously switching output", Rob
      • Re: "simultaneously switching output", Symon
• RAM32X1D and Virtex-5, Rob
• Spartan 3e and SDRAM, Alex Freed
  • Re: Spartan 3e and SDRAM, ghelbig
    • Re: Spartan 3e and SDRAM, Alex Freed
• BUFGCE, u_stadler@xxxxxxxx
  • Re: BUFGCE, John_H
    • Re: BUFGCE, u_stadler@xxxxxxxx
    • Re: BUFGCE, David Spencer
      • Re: BUFGCE, u_stadler@xxxxxxxx
      • Re: BUFGCE, John_H
• Re: EDK IPIF development workflow, comp.arch.fpga
• clock cycle per Instructions, fazulu deen
  • Re: clock cycle per Instructions, RCIngham
• converting verilog to vhdl, Anuja
  • Re: converting verilog to vhdl, Eric Smith
    • Re: converting verilog to vhdl, Anuja
      • Re: converting verilog to vhdl, RCIngham
      • Re: converting verilog to vhdl, Anuja
      • Re: converting verilog to vhdl, RCIngham
      • Re: converting verilog to vhdl, Anuja
      • Re: converting verilog to vhdl, Andy
      • Re: converting verilog to vhdl, Anuja
      • Re: converting verilog to vhdl, Anuja
      • Re: converting verilog to vhdl, Anuja
  • Re: converting verilog to vhdl, Matthew Hicks
  • Re: converting verilog to vhdl, Dave
    • Re: converting verilog to vhdl, Anuja
• clock lines, axr0284
  • Re: clock lines, John_H
    • Re: clock lines, axr0284
      • Re: clock lines, Goli
      • Re: clock lines, PatC
      • Re: clock lines, Marc Randolph
• Can't get Quartus to Infer Dual Port Ram for Stratix2GX, General Schvantzkopf
  • Re: Can't get Quartus to Infer Dual Port Ram for Stratix2GX, Tommy Thorn
    • Re: Can't get Quartus to Infer Dual Port Ram for Stratix2GX, General Schvantzkopf
• UK FPGA supplier, dbeck88
• XILINX XABEL, Michael Laajanen
  • Re: XILINX XABEL, Jim Granville
    • Re: XILINX XABEL, Michael Laajanen
• EDK does not find Modelsim, Timo Gerber
  • Re: EDK does not find Modelsim, Mike Treseler
• calculation of clock cycle /instructions..., fazulu deen
  • Re: calculation of clock cycle /instructions..., Mike Treseler
  • Re: calculation of clock cycle /instructions..., Nico Coesel
• Xilinx Platform USB Cable, Andrew Ganger
  • Re: Xilinx Platform USB Cable, Symon
  • Re: Xilinx Platform USB Cable, Eric Smith
• Power PC ISOCM Simulation, motty
• Virtex5: LVCMOS33 and LVDS_25 inputs (with DIFF_TERM) in same bank?, Barry
  • Re: Virtex5: LVCMOS33 and LVDS_25 inputs (with DIFF_TERM) in same bank?, John_H
  • Re: Virtex5: LVCMOS33 and LVDS_25 inputs (with DIFF_TERM) in same bank?, Sean Durkin
    • Re: Virtex5: LVCMOS33 and LVDS_25 inputs (with DIFF_TERM) in same bank?, Barry
  • Re: Virtex5: LVCMOS33 and LVDS_25 inputs (with DIFF_TERM) in same bank?, Symon
    • Re: Virtex5: LVCMOS33 and LVDS_25 inputs (with DIFF_TERM) in same bank?, Barry
      • Re: Virtex5: LVCMOS33 and LVDS_25 inputs (with DIFF_TERM) in same bank?, Symon
• Re: lossless compression in hardware: what to do in case of uncompressibility?, RCIngham
• Xilinx ISE Bugs, Mike
  • Re: Xilinx ISE Bugs, comp.arch.fpga
  • Re: Xilinx ISE Bugs, Joseph Samson
  • Re: Xilinx ISE Bugs, John Retta
• Re: What's the difference for VHDL code between simulation and synthesis?, Martin Thompson
  • Re: What's the difference for VHDL code between simulation and synthesis?, KJ
    • Re: What's the difference for VHDL code between simulation and synthesis?, Martin Thompson
      • Re: What's the difference for VHDL code between simulation and synthesis?, KJ
      • Re: What's the difference for VHDL code between simulation and synthesis?, Mike Treseler
  • <Possible follow-ups>
  • Re: What's the difference for VHDL code between simulation and synthesis?, rickman
    • Re: What's the difference for VHDL code between simulation and synthesis?, KJ
      • Re: What's the difference for VHDL code between simulation and synthesis?, rickman
      • Re: What's the difference for VHDL code between simulation and synthesis?, Andy
      • Re: What's the difference for VHDL code between simulation and synthesis?, rickman
      • Re: What's the difference for VHDL code between simulation and synthesis?, Mike Treseler
      • Re: What's the difference for VHDL code between simulation and synthesis?, rickman
  • Re: What's the difference for VHDL code between simulation and synthesis?, Mike Treseler
    • Re: What's the difference for VHDL code between simulation and synthesis?, rickman
      • Re: What's the difference for VHDL code between simulation and synthesis?, Mike Treseler
      • Re: What's the difference for VHDL code between simulation and synthesis?, rickman
      • Re: What's the difference for VHDL code between simulation and synthesis?, Mike Treseler
      • Re: What's the difference for VHDL code between simulation and synthesis?, Andy
      • Re: What's the difference for VHDL code between simulation and synthesis?, rickman
      • Re: What's the difference for VHDL code between simulation and synthesis?, Mike Treseler
  • Re: What's the difference for VHDL code between simulation and synthesis?, glen herrmannsfeldt
    • Re: What's the difference for VHDL code between simulation and synthesis?, KJ
      • Re: What's the difference for VHDL code between simulation and synthesis?, glen herrmannsfeldt
      • Re: What's the difference for VHDL code between simulation and synthesis?, Ray Andraka
      • Re: What's the difference for VHDL code between simulation and synthesis?, glen herrmannsfeldt
      • Re: What's the difference for VHDL code between simulation and synthesis?, Ray Andraka
      • Re: What's the difference for VHDL code between simulation and synthesis?, KJ
      • Re: What's the difference for VHDL code between simulation and synthesis?, Ray Andraka
      • Re: What's the difference for VHDL code between simulation and synthesis?, Andy
      • Re: What's the difference for VHDL code between simulation and synthesis?, KJ
      • Re: What's the difference for VHDL code between simulation and synthesis?, Mike Treseler
• Re: ise timing analysis + different clock domains, PatC
  • Re: ise timing analysis + different clock domains, u_stadler@xxxxxxxx
• Re: Asynchronous FIFO and almost empty - bug?, PatC
  • Re: Asynchronous FIFO and almost empty - bug?, Peter Alfke
    • Re: Asynchronous FIFO and almost empty - bug?, heinerlitz@xxxxxxxxxxxxxx
• Researching Reconfigurable Computing, lyonscf
  • Re: Researching Reconfigurable Computing, Jecel
    • Re: Researching Reconfigurable Computing, lyonscf@xxxxxxxxx
• Memec Flancter app note?, Eric Smith
  • Re: Memec Flancter app note?, Eric Smith
• Re: Fedora 8 and ISE 9.2, Michael Laajanen
  • Re: Fedora 8 and ISE 9.2, Eric Smith
    • Re: Fedora 8 and ISE 9.2, pdudley1@xxxxxxxxxxx
• XHwICAP functions on EDK, hiroyuki.kawai0914@xxxxxxxxx
• Re: Interfacing Cyclone III to 3.3v LVDS devices, cms
  • <Possible follow-ups>
  • Re: Interfacing Cyclone III to 3.3v LVDS devices, LC
    • Re: Interfacing Cyclone III to 3.3v LVDS devices, MikeShepherd564
• can't genarate block memory cores in ISE 7.1i, blisca
  • R: can't genarate block memory cores in ISE 7.1i, blisca
  • Re: can't genarate block memory cores in ISE 7.1i, argee
  • Re: can't genarate block memory cores in ISE 7.1i, Mike Treseler
    • Re: can't genarate block memory cores in ISE 7.1i, blisca
• Re: Pipelining of FPGA code, dash82
• What option can change the path sign "\" in Quartus ?, fl
  • Re: What option can change the path sign "\" in Quartus ?, fl
    • Re: What option can change the path sign "\" in Quartus ?, cms
    • Re: What option can change the path sign "\" in Quartus ?, cms
• Re: Drawing timing-diagrams for documentation, Sean Durkin
• Using SRAM Memory CY7C1386C, create
  • Re: Using SRAM Memory CY7C1386C, Duane Clark
  • Re: Using SRAM Memory CY7C1386C, Ben Jackson
• Configuration via JTAG using an Embedded Controller, shunsl
  • Re: Configuration via JTAG using an Embedded Controller, ghelbig
• Re: area group constraint problem (more detailed) - solved, l.s.rockfan@xxxxxx
• Re: Using DDR RAM on XUP V2Pro board, David Binnie
  • Re: Using DDR RAM on XUP V2Pro board, marek . kraft
    • Re: Using DDR RAM on XUP V2Pro board, Duane Clark
    • Re: Using DDR RAM on XUP V2Pro board, David Binnie
• Re: Traffic Light with counter, Dave
  • <Possible follow-ups>
  • Re: Traffic Light with counter, Symon
    • Re: Traffic Light with counter, Jonathan Bromley
    • Re: Traffic Light with counter, tang
    • Re: Traffic Light with counter, Mike Treseler
      • Re: Traffic Light with counter, Jonathan Bromley
      • Re: Traffic Light with counter, KJ
      • Re: Traffic Light with counter, Symon
  • Re: Traffic Light with counter, John Adair
    • Re: Traffic Light with counter, tang
      • Re: Traffic Light with counter, Marlboro
      • Re: Traffic Light with counter, John Adair

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