comp.arch.fpga

• Date Index

---

• Traffic Light with counter, tang
• Christmas and New Year at Enterpoint, John Adair
• ise timing analysis + different clock domains, u_stadler@xxxxxxxx
  • Re: ise timing analysis + different clock domains, Mike Treseler
• Using DDR RAM on XUP V2Pro board, marek . kraft
• Pipelining of FPGA code, dash82
  • Re: Pipelining of FPGA code, KJ
    • Re: Pipelining of FPGA code, glen herrmannsfeldt
  • Re: Pipelining of FPGA code, RCIngham
  • Re: Pipelining of FPGA code, Symon
• EDK 9.2 Woes, motty
  • Re: EDK 9.2 Woes, John Williams
    • Re: EDK 9.2 Woes, motty
• EDK IPIF development workflow, Anton Kowalski
  • Re: EDK IPIF development workflow, John McCaskill
• Hand solder that FPGA on your prototype, Tony Burch
  • Re: Hand solder that FPGA on your prototype, Chris Maryan
    • Re: Hand solder that FPGA on your prototype, Tony Burch
      • Re: Hand solder that FPGA on your prototype, MikeShepherd564
  • Re: Hand solder that FPGA on your prototype, Nico Coesel
• Drawing timing-diagrams for documentation, Sean Durkin
  • Re: Drawing timing-diagrams for documentation, Chris Maryan
• Asynchronous FIFO and almost empty - bug?, heinerlitz@xxxxxxxxxxxxxx
  • Re: Asynchronous FIFO and almost empty - bug?, Peter Alfke
    • Re: Asynchronous FIFO and almost empty - bug?, heinerlitz@xxxxxxxxxxxxxx
      • Re: Asynchronous FIFO and almost empty - bug?, Peter Alfke
      • Re: Asynchronous FIFO and almost empty - bug?, Peter Alfke
      • Re: Asynchronous FIFO and almost empty - bug?, Peter Alfke
  • Re: Asynchronous FIFO and almost empty - bug?, Peter Alfke
• Cascaded DCMs with variable phase shift (Xilinx), chesi
  • Re: Cascaded DCMs with variable phase shift (Xilinx), austin
    • Re: Cascaded DCMs with variable phase shift (Xilinx), chesi
  • Re: Cascaded DCMs with variable phase shift (Xilinx), austin
• Interfacing Cyclone III to 3.3v LVDS devices, liqiyue@xxxxxxxxx
• Quartus memory init file, Mark McDougall
  • Re: Quartus memory init file, MikeShepherd564
    • Re: Quartus memory init file, Mark McDougall
      • Re: Quartus memory init file, John Rible
      • Re: Quartus memory init file, Mark McDougall
• System ACE debug, cpandya
• Re: What tools do you use ? Why ?, RCIngham
• Re: SLICEL : 92%,SLICEM 2%, Jim Wu
• FPGA not in boundary scan, Mike
  • Re: FPGA not in boundary scan, John_H
    • Re: FPGA not in boundary scan, Mike
      • Re: FPGA not in boundary scan, John_H
      • Re: FPGA not in boundary scan, Mike
    • Re: FPGA not in boundary scan, Mike
      • Re: FPGA not in boundary scan, Mike
      • Re: FPGA not in boundary scan, John_H
• Adding Desing to an Xilins Platform Studio project, Timo Gerber
• Gnd plane coupling with DDR routing from FPGA <-> DDR?, Nial Stewart
  • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, Brian Drummond
  • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, austin
    • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, Nial Stewart
  • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, David Spencer
    • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, Nial Stewart
      • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, David Spencer
  • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, Nico Coesel
  • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, KJ
    • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, Nial Stewart
      • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, KJ
  • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, Symon
    • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, David Spencer
      • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, Nial Stewart
      • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, KJ
      • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, Symon
      • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, John Larkin
      • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, Symon
      • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, Nial Stewart
      • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, Symon
      • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, John Larkin
      • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, Nial Stewart
      • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, John Larkin
    • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, Nial Stewart
      • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, Symon
  • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, Jon Elson
    • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, Nial Stewart
  • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, Didi
    • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, Didi
    • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, Nial Stewart
      • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, Didi
    • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, David Spencer
      • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, Didi
      • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, Symon
      • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, David Spencer
      • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, Didi
  • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, John Larkin
    • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, Nial Stewart
      • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, John Larkin
  • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, John Adair
    • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, Nial Stewart
      • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?, Symon
• DDR2 controler, bhb
  • Re: DDR2 controler, Helmut
    • Re: DDR2 controler, jacobusn@xxxxxxxxxx
• I/O short circuit protection?, posedge52
  • Re: I/O short circuit protection?, Jim Granville
    • Re: I/O short circuit protection?, posedge52
      • Re: I/O short circuit protection?, David Spencer
  • Re: I/O short circuit protection?, John_H
    • Re: I/O short circuit protection?, posedge52
• Behavioral Simulation working but Post-route Simulation is not., andyto@xxxxxxxxx
  • Re: Behavioral Simulation working but Post-route Simulation is not., mk
    • Re: Behavioral Simulation working but Post-route Simulation is not., andyto@xxxxxxxxx
      • Re: Behavioral Simulation working but Post-route Simulation is not., mh
      • Re: Behavioral Simulation working but Post-route Simulation is not., KJ
• device utilization, fazulu deen
• area group constraint problem, L. Schreiber
  • Re: area group constraint problem, Matthew Hicks
    • Re: area group constraint problem, mh
  • Re: area group constraint problem (more detailed), L. Schreiber
• Xilinx IO leakage when not powered, dipumisc
  • Re: Xilinx IO leakage when not powered, Peter Alfke
  • Re: Xilinx IO leakage when not powered, austin
• What's the difference for VHDL code between simulation and synthesis?, fl
  • Re: What's the difference for VHDL code between simulation and synthesis?, KJ
  • Re: What's the difference for VHDL code between simulation and synthesis?, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
    • Re: What's the difference for VHDL code between simulation and synthesis?, Mike Treseler
    • Re: What's the difference for VHDL code between simulation and synthesis?, KJ
  • Re: What's the difference for VHDL code between simulation and synthesis?, rickman
    • Re: What's the difference for VHDL code between simulation and synthesis?, KJ
• Fedora 8 and ISE 9.2, Michael Laajanen
  • Re: Fedora 8 and ISE 9.2, Thomas Feller
• CPU design uses too many slices, Jürgen Böhm
  • Re: CPU design uses too many slices, Jon Elson
    • Re: CPU design uses too many slices, Gabor
    • Re: CPU design uses too many slices, Jürgen Böhm
      • Re: CPU design uses too many slices, Jon Elson
  • Re: CPU design uses too many slices, Jim Granville
    • Re: CPU design uses too many slices, Jürgen Böhm
      • Re: CPU design uses too many slices, rickman
      • Re: CPU design uses too many slices, Jürgen Böhm
      • Re: CPU design uses too many slices, rickman
      • Re: CPU design uses too many slices, glen herrmannsfeldt
      • Re: CPU design uses too many slices, Brian Drummond
      • Re: CPU design uses too many slices, Jon Elson
      • Re: CPU design uses too many slices, Eric Smith
      • Re: CPU design uses too many slices, Jürgen Böhm
      • Re: CPU design uses too many slices, rickman
      • Re: CPU design uses too many slices, Jürgen Böhm
      • Re: CPU design uses too many slices, rickman
      • Re: CPU design uses too many slices, Peter Alfke
  • Re: CPU design uses too many slices, Joseph Samson
• Xilinx Multilink Connection not working, Philipp
  • Re: Xilinx Multilink Connection not working, Philipp
    • Re: Xilinx Multilink Connection not working, mh
• Global Reset using Global Buffer, rgamer1981@xxxxxxxxx
  • Re: Global Reset using Global Buffer, austin
    • Re: Global Reset using Global Buffer, Rgamer
      • Re: Global Reset using Global Buffer, austin
      • Re: Global Reset using Global Buffer, Eric Smith
      • Re: Global Reset using Global Buffer, Ed McGettigan
      • Re: Global Reset using Global Buffer, Eric Smith
      • Re: Global Reset using Global Buffer, Rgamer
      • Re: Global Reset using Global Buffer, John_H
      • Re: Global Reset using Global Buffer, Jim Wu
      • Re: Global Reset using Global Buffer, Rgamer
      • Re: Global Reset using Global Buffer, Andrew FPGA
      • Re: Global Reset using Global Buffer, Eric Smith
      • Re: Global Reset using Global Buffer, Rgamer
      • Re: Global Reset using Global Buffer, RCIngham
      • Re: Global Reset using Global Buffer, neilla
      • Re: Global Reset using Global Buffer, Brian Drummond
      • Re: Global Reset using Global Buffer, Rgamer
      • Re: Global Reset using Global Buffer, austin
• yet another Altera Cyclone II EP2C35 dev. board, fpga-dev
  • Re: yet another Altera Cyclone II EP2C35 dev. board, Ben Jackson
    • Re: yet another Altera Cyclone II EP2C35 dev. board, fpga-dev
  • Re: yet another Altera Cyclone II EP2C35 dev. board, Tommy Thorn
    • Re: yet another Altera Cyclone II EP2C35 dev. board, fpga-dev
• Xilinx XChecker cable supported until which version?, Florian
  • Re: Xilinx XChecker cable supported until which version?, Neil Glenn Jacobson
• how to generate a linker script?, xenix
• Bidirectional open drain port, fazulu deen
• scanf and printf in EDK's BSP, rha_x
  • Re: scanf and printf in EDK's BSP, Matthew Hicks
    • Re: scanf and printf in EDK's BSP, rha_x
      • Re: scanf and printf in EDK's BSP, Matthew Hicks
      • Re: scanf and printf in EDK's BSP, Andreas Hofmann
  • Re: scanf and printf in EDK's BSP, Brian Drummond
    • Re: scanf and printf in EDK's BSP, rha_x
• Spare Spartan3's, Daveb
• ISE and Itanium, GaLaKtIkUs(tm)
  • Re: ISE and Itanium, EEngineer
• Hook open drain "power good" to nSTATUS or nCONFIG?, Ben Jackson
  • Re: Hook open drain "power good" to nSTATUS or nCONFIG?, Allan Herriman
    • Re: Hook open drain "power good" to nSTATUS or nCONFIG?, Allan Herriman
      • Re: Hook open drain "power good" to nSTATUS or nCONFIG?, Allan Herriman
  • Re: Hook open drain "power good" to nSTATUS or nCONFIG?, Eli Bendersky
• Converting a ByteBlasterMV into a ByteBlaster II?, Nevo
  • Re: Converting a ByteBlasterMV into a ByteBlaster II?, ghelbig
  • Re: Converting a ByteBlasterMV into a ByteBlaster II?, Ben Jackson
  • Re: Converting a ByteBlasterMV into a ByteBlaster II?, David Spencer
• Xilinx Dual processor design, naresh
  • Re: Xilinx Dual processor design, Ben Jackson
  • Re: Xilinx Dual processor design, Andreas Hofmann
• Start-up Xilkernel on Microblaze, Yannick
  • Re: Start-up Xilkernel on Microblaze, Vasanth Asokan
    • Re: Start-up Xilkernel on Microblaze, Yannick
• using fpga as programmable connection, joe
  • Re: using fpga as programmable connection, Jonathan Bromley
    • Re: using fpga as programmable connection, joe
      • Re: using fpga as programmable connection, KJ
  • Re: using fpga as programmable connection, Jim Granville
  • Re: using fpga as programmable connection, glen herrmannsfeldt
• Fifo Block-RAM Xilinx ISE - port empty, zlotawy
• vhdl state machine, nbg2006
  • Re: vhdl state machine, Jonathan Bromley
  • Re: vhdl state machine, Mike Treseler
• can't read/load memory contents, dartanian
  • Re: can't read/load memory contents, Minh Nguyen
    • Re: can't read/load memory contents, dartanian
    • Re: can't read/load memory contents, dartanian
      • Re: can't read/load memory contents, Minh Nguyen
      • Re: can't read/load memory contents, dartanian
      • Re: can't read/load memory contents, Minh Nguyen
      • Re: can't read/load memory contents, glen herrmannsfeldt
• xilinx spartan 3 + 16 adc, wojjed
  • Re: xilinx spartan 3 + 16 adc, jerzy.gbur@xxxxxxxxx
    • Re: xilinx spartan 3 + 16 adc, wojjed
      • Re: xilinx spartan 3 + 16 adc, taco
      • Re: xilinx spartan 3 + 16 adc, MM
      • Re: xilinx spartan 3 + 16 adc, Peter Alfke
      • Re: xilinx spartan 3 + 16 adc, Jim Granville
      • Re: xilinx spartan 3 + 16 adc, Brian Drummond
      • Re: xilinx spartan 3 + 16 adc, MM
• Registrations open for VLSI Conference 2008 in Hyderabad, India, gdbansal
• Virtex 5 PCB Designers Guide: required capacitors, michel . talon
  • Re: Virtex 5 PCB Designers Guide: required capacitors, Symon
• React on falling edge in testbench, Timo Gerber
  • Re: React on falling edge in testbench, Jonathan Bromley
    • Re: React on falling edge in testbench, Timo Gerber
• converter, dilip
  • Re: converter, Jonathan Bromley
  • Re: converter, glen herrmannsfeldt
    • Re: converter, Mike Treseler
• PCI Mezzanine Card with Xilinx Virtex-II, Philipp
  • Re: PCI Mezzanine Card with Xilinx Virtex-II, colin
    • Re: PCI Mezzanine Card with Xilinx Virtex-II, Philipp
    • Re: PCI Mezzanine Card with Xilinx Virtex-II, Philipp
  • Re: PCI Mezzanine Card with Xilinx Virtex-II, cmoore
  • Re: PCI Mezzanine Card with Xilinx Virtex-II, Ben Jackson
• DDR2 dqs pin // virtex4, bhb
  • Re: DDR2 dqs pin // virtex4, Joseph Samson
    • Re: DDR2 dqs pin // virtex4, bhb
      • Re: DDR2 dqs pin // virtex4, Joseph Samson
      • Re: DDR2 dqs pin // virtex4, bhb
• DCM with instable clock, wxy0624
  • Re: DCM with instable clock, Hal Murray
    • Re: DCM with instable clock, wxy0624
    • Re: DCM with instable clock, wxy0624
      • Re: DCM with instable clock, Peter Alfke
      • Re: DCM with instable clock, wxy0624
      • Re: DCM with instable clock, Peter Alfke
      • Re: DCM with instable clock, wxy0624
      • Re: DCM with instable clock, Barry
      • Re: DCM with instable clock, austin
      • Re: DCM with instable clock, wxy0624
      • Re: DCM with instable clock, austin
• Unable to scan device chain, Nevo
  • Re: Unable to scan device chain, rickman
  • Re: Unable to scan device chain, John_H
    • Re: Unable to scan device chain, Nevo
  • Re: Unable to scan device chain, Nevo
  • Re: Unable to scan device chain, Andre
    • Re: Unable to scan device chain, Nevo
      • Re: Unable to scan device chain, Nevo
• EDK + Modelsim simulation : Memory allocation failure, Pasacco
  • Re: EDK + Modelsim simulation : Memory allocation failure, John McCaskill
    • Re: EDK + Modelsim simulation : Memory allocation failure, Pasacco
      • Re: EDK + Modelsim simulation : Memory allocation failure, Kim Enkovaara
      • Re: EDK + Modelsim simulation : Memory allocation failure, Pasacco
• Measuring setup and hold time in Lab, Ved
  • Re: Measuring setup and hold time in Lab, MikeShepherd564
  • Re: Measuring setup and hold time in Lab, John_H
  • Re: Measuring setup and hold time in Lab, David Spencer
  • Re: Measuring setup and hold time in Lab, Jim Granville
    • Re: Measuring setup and hold time in Lab, David Spencer
      • Re: Measuring setup and hold time in Lab, Jim Granville
  • Re: Measuring setup and hold time in Lab, glen herrmannsfeldt
    • Re: Measuring setup and hold time in Lab, Mike Lewis
  • Re: Measuring setup and hold time in Lab, Peter Alfke
• Xilinx XST 8.2, Error on multi-source, bug?, Timo Gerber
  • Re: Xilinx XST 8.2, Error on multi-source, bug?, John McCaskill
    • Re: Xilinx XST 8.2, Error on multi-source, bug?, Gabor
  • Re: Xilinx XST 8.2, Error on multi-source, bug?, Brian Drummond
  • Re: Xilinx XST 8.2, Error on multi-source, bug?, Timo Gerber
• partial dynamic reconfiguration on Virtex-4 SX35, G_Abg
  • Re: partial dynamic reconfiguration on Virtex-4 SX35, rickman
    • Re: partial dynamic reconfiguration on Virtex-4 SX35, G_Abg
      • Re: partial dynamic reconfiguration on Virtex-4 SX35, rickman
      • Re: partial dynamic reconfiguration on Virtex-4 SX35, mh
  • Re: partial dynamic reconfiguration on Virtex-4 SX35, austin
    • Re: partial dynamic reconfiguration on Virtex-4 SX35, G_Abg
• An error occured while using Dual Port Block Memory, spygame81
  • Re: An error occured while using Dual Port Block Memory, Joseph Samson
    • Re: An error occured while using Dual Port Block Memory, RAI
• FPGA Editor (9.2.03i) under Linux x86_64, Jan Pech
  • Re: FPGA Editor (9.2.03i) under Linux x86_64, steve.lass
    • Re: FPGA Editor (9.2.03i) under Linux x86_64, krishnans
    • Re: FPGA Editor (9.2.03i) under Linux x86_64, Uwe Bonnes
    • Re: FPGA Editor (9.2.03i) under Linux x86_64, rickman
      • Re: FPGA Editor (9.2.03i) under Linux x86_64, Andrew Greensted
      • Re: FPGA Editor (9.2.03i) under Linux x86_64, steve.lass
      • Re: FPGA Editor (9.2.03i) under Linux x86_64, rickman
      • Re: FPGA Editor (9.2.03i) under Linux x86_64, rickman
• Why doesnt XST RAM for this VHDL description, Philipp
  • Re: Why doesnt XST RAM for this VHDL description, mk
    • Re: Why doesnt XST RAM for this VHDL description, Philipp
      • Re: Why doesnt XST RAM for this VHDL description, Philipp
• Xilinx Virtex 5 ISERDES vs ISERDES_NODELAY: which is better for DDR?, Barry
• Virtex5 Evaluation Board, Philipp
  • Re: Virtex5 Evaluation Board, austin
    • Re: Virtex5 Evaluation Board, Philipp
      • Re: Virtex5 Evaluation Board, John Adair
      • Re: Virtex5 Evaluation Board, John Adair
• EDK 9.2 and virtex 2 devices, Andreas Wassatsch
  • Re: EDK 9.2 and virtex 2 devices, Harald
    • Re: EDK 9.2 and virtex 2 devices, Andreas Wassatsch
      • Re: EDK 9.2 and virtex 2 devices, Harald
      • Re: EDK 9.2 and virtex 2 devices, Philip Potter
      • Re: EDK 9.2 and virtex 2 devices, Harald
      • Re: EDK 9.2 and virtex 2 devices, Andreas Wassatsch
      • Re: EDK 9.2 and virtex 2 devices, Harald
      • Re: EDK 9.2 and virtex 2 devices, Andreas Wassatsch
      • Re: EDK 9.2 and virtex 2 devices, Harald
      • Re: EDK 9.2 and virtex 2 devices, Harald
      • Re: EDK 9.2 and virtex 2 devices, Philip Potter
      • Re: EDK 9.2 and virtex 2 devices, Andreas Wassatsch
• problem with adding custom logic to an IP core (xilinx edk), techG
  • Re: problem with adding custom logic to an IP core (xilinx edk), Andrew Greensted
  • Re: problem with adding custom logic to an IP core (xilinx edk), Jeff Cunningham
  • Re: problem with adding custom logic to an IP core (xilinx edk), Matthew Hicks
• 33+ Regs in PLB IPIF, Matthew Hicks
  • Re: 33+ Regs in PLB IPIF, Joseph Samson
    • Re: 33+ Regs in PLB IPIF, Matthew Hicks
      • Re: 33+ Regs in PLB IPIF, Jason Agron
      • Re: 33+ Regs in PLB IPIF, Matthew Hicks
• Parallel to Serial ASI ..., Kappa
  • Re: Parallel to Serial ASI ..., austin
    • Re: Parallel to Serial ASI ..., Kappa
• TPS75003 Spartan-3(E) Regulator Design, Andrew Greensted
  • Re: TPS75003 Spartan-3(E) Regulator Design, Laurent Pinchart
    • Re: TPS75003 Spartan-3(E) Regulator Design, Andrew Greensted
    • Re: TPS75003 Spartan-3(E) Regulator Design, Andrew Greensted
  • Re: TPS75003 Spartan-3(E) Regulator Design, John Adair
    • Re: TPS75003 Spartan-3(E) Regulator Design, Symon
• Microblaze books, xenix
  • Re: Microblaze books, ghelbig
    • Re: Microblaze books, Jeff Cunningham
  • Re: Microblaze books, svenand
• Update to Xilinx ISE 9.2, Harald
  • Re: Update to Xilinx ISE 9.2, Dave
    • Re: Update to Xilinx ISE 9.2, Harald
      • Re: Update to Xilinx ISE 9.2, ghelbig
      • Re: Update to Xilinx ISE 9.2, Harald
      • Re: Update to Xilinx ISE 9.2, Andreas Hofmann
• Re: VHDL language is out of date! Why? I will explain., RCIngham
  • <Possible follow-ups>
  • Re: VHDL language is out of date! Why? I will explain., RCIngham
  • Re: VHDL language is out of date! Why? I will explain., MikeShepherd564
• mb-g++ linker script problem 8.2i, Bathala
  • Re: mb-g++ linker script problem 8.2i, Alan Nishioka
• Xilinx WebPack 9.2i: Download not possible, wrong links, Udo
• synthesizing vqm with parameters with quartus 7.1sp1, hershkoy
  • Re: synthesizing vqm with parameters with quartus 7.1sp1, KJ
• Altera webpack for Linux?, radarman
  • Re: Altera webpack for Linux?, Uwe Bonnes
  • Message not available
    • Re: Altera webpack for Linux?, radarman
• Quartus II warning: "pass-through logic has been added", Tommy Thorn
  • Re: Quartus II warning: "pass-through logic has been added", KJ
    • Re: Quartus II warning: "pass-through logic has been added", Hal Murray
      • Re: Quartus II warning: "pass-through logic has been added", KJ
      • Re: Quartus II warning: "pass-through logic has been added", rickman
      • Re: Quartus II warning: "pass-through logic has been added", KJ
      • Re: Quartus II warning: "pass-through logic has been added", Tommy Thorn
      • Re: Quartus II warning: "pass-through logic has been added", Hal Murray
      • Re: Quartus II warning: "pass-through logic has been added", KJ
      • Re: Quartus II warning: "pass-through logic has been added", mk
      • Re: Quartus II warning: "pass-through logic has been added", MikeShepherd564
  • Re: Quartus II warning: "pass-through logic has been added", glen herrmannsfeldt
  • Re: Quartus II warning: "pass-through logic has been added", Mike Treseler
• Coolrunner in system programming - XAPP0058 - viable?, Didi
  • Re: Coolrunner in system programming - XAPP0058 - viable?, Jim Granville
    • Re: Coolrunner in system programming - XAPP0058 - viable?, Didi
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Jim Granville
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Didi
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Jim Granville
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Didi
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Jim Granville
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Didi
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Jim Granville
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Didi
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Jim Granville
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Didi
  • Re: Coolrunner in system programming - XAPP0058 - viable?, Didi
    • Re: Coolrunner in system programming - XAPP0058 - viable?, Antonio Pasini
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Jim Granville
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Antonio Pasini
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Didi
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Antonio Pasini
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Jim Granville
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Didi
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Didi
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Jim Granville
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Didi
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Jim Granville
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Didi
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Eric Smith
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Didi
  • Re: Coolrunner in system programming - XAPP0058 - viable?, colin
    • Re: Coolrunner in system programming - XAPP0058 - viable?, Didi
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Jim Granville
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Didi
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Didi
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Jim Granville
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Jim Granville
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Didi
      • Re: Coolrunner in system programming - XAPP0058 - viable?, rickman
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Didi
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Jim Granville
      • Re: Coolrunner in system programming - XAPP0058 - viable?, rickman
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Jim Granville
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Didi
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Alex
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Didi
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Didi
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Jim Granville
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Peter Alfke
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Didi
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Jim Granville
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Hal Murray
      • Re: Coolrunner in system programming - XAPP0058 - viable?, Jim Granville
• how to KEEP_HIERARCHY [EDK], Pasacco
  • Re: how to KEEP_HIERARCHY [EDK], Andreas Hofmann
• gate count calculation in xilinx., subbu
  • <Possible follow-ups>
  • Gate count calculation in xilinx., subbu
    • Re: Gate count calculation in xilinx., Peter Alfke
• New Laptop for work, rickman
  • Re: New Laptop for work, evilkidder@xxxxxxxxxxxxxx
  • Re: New Laptop for work, HT-Lab
    • Message not available
      • Re: New Laptop for work, HT-Lab
      • Re: New Laptop for work, rickman
      • Re: New Laptop for work, Andreas Hofmann
  • Re: New Laptop for work, Guru
    • Re: New Laptop for work, rickman
  • Re: New Laptop for work, General Schvantzkoph
    • Re: New Laptop for work, rickman
• Re: jitter-sensitive multi-output clk distribution for multi-gigabit-transceivers, Symon
• simulating xilinx block ram with modelsim, u_stadler@xxxxxxxx
  • Re: simulating xilinx block ram with modelsim, Duane Clark
    • Re: simulating xilinx block ram with modelsim, Andrew Ganger
      • Re: simulating xilinx block ram with modelsim, Duane Clark
    • Re: simulating xilinx block ram with modelsim, u_stadler@xxxxxxxx
      • Re: simulating xilinx block ram with modelsim, Duane Clark
  • Re: simulating xilinx block ram with modelsim, Mike Treseler
    • Re: simulating xilinx block ram with modelsim, Peter Alfke
      • Re: simulating xilinx block ram with modelsim, u_stadler@xxxxxxxx
      • Re: simulating xilinx block ram with modelsim, John Retta
      • Re: simulating xilinx block ram with modelsim, u_stadler@xxxxxxxx
      • Re: simulating xilinx block ram with modelsim, Brian Drummond
      • Re: simulating xilinx block ram with modelsim, u_stadler@xxxxxxxx
      • Re: simulating xilinx block ram with modelsim, Brian Drummond
      • Re: simulating xilinx block ram with modelsim, u_stadler@xxxxxxxx
      • Re: simulating xilinx block ram with modelsim, Brian Drummond
      • Re: simulating xilinx block ram with modelsim, Duane Clark
• TI DSP soft core in Xilinx?, cpope
  • Re: TI DSP soft core in Xilinx?, David Spencer
    • Re: TI DSP soft core in Xilinx?, cpope
    • Re: TI DSP soft core in Xilinx?, Guenter Dannoritzer
    • Re: TI DSP soft core in Xilinx?, austin
      • Re: TI DSP soft core in Xilinx?, cpope
• Lattice Semi, Colin Hankins
  • Re: Lattice Semi, John_H
  • Re: Lattice Semi, lb . edc
  • Re: Lattice Semi, Jon Beniston
  • Low cost FPGA w/serdes, austin
    • Re: Low cost FPGA w/serdes, lb . edc
      • Re: Low cost FPGA w/serdes, austin
      • Re: Low cost FPGA w/serdes, MK
      • Re: Low cost FPGA w/serdes, austin
      • Re: Low cost FPGA w/serdes, MikeShepherd564
      • Re: Low cost FPGA w/serdes, austin
      • Re: Low cost FPGA w/serdes, Will Dean
      • Re: Low cost FPGA w/serdes, austin
      • Re: Low cost FPGA w/serdes, Jonathan Bromley
      • Re: Low cost FPGA w/serdes, austin
      • Re: Low cost FPGA w/serdes, Jonathan Bromley
      • Re: Low cost FPGA w/serdes, lb . edc
      • Re: Low cost FPGA w/serdes, austin
  • Message not available
    • Re: Lattice Semi, John_H
• V4FX: Cannot access EMAC1 of Dual MAC system, JimboD2
  • Re: V4FX: Cannot access EMAC1 of Dual MAC system, JimboD2
  • Re: V4FX: Cannot access EMAC1 of Dual MAC system, Ben Jackson
    • Re: V4FX: Cannot access EMAC1 of Dual MAC system, JimboD2
      • Re: V4FX: Cannot access EMAC1 of Dual MAC system, Ben Jackson
      • Re: V4FX: Cannot access EMAC1 of Dual MAC system, JimboD2
      • Re: V4FX: Cannot access EMAC1 of Dual MAC system, JimboD2
• EDK 9.1 Issues, Matthew Hicks
  • Re: EDK 9.1 Issues, Philip Potter
    • Re: EDK 9.1 Issues, Matthew Hicks
  • Re: EDK 9.1 Issues, Daniel Koethe
    • Re: EDK 9.1 Issues, Matthew Hicks
  • Re: EDK 9.1 Issues, Duane Clark
    • Re: EDK 9.1 Issues, Matthew Hicks
• Xilinx Chipscope Pro in EDK system - ILA:how specify separate signals for data capture and triggering?, Andrew FPGA
  • Re: Xilinx Chipscope Pro in EDK system - ILA:how specify separate signals for data capture and triggering?, roger
    • Re: Xilinx Chipscope Pro in EDK system - ILA:how specify separate signals for data capture and triggering?, Andrew FPGA
• Block-ram FIFO in Xilinx, zlotawy
  • Re: Block-ram FIFO in Xilinx, Peter Alfke
    • Re: Block-ram FIFO in Xilinx, ghelbig
      • Re: Block-ram FIFO in Xilinx, Peter Alfke
    • Re: Block-ram FIFO in Xilinx, zlotawy
      • Re: Block-ram FIFO in Xilinx, Peter Alfke
      • Re: Block-ram FIFO in Xilinx, zlotawy
      • Re: Block-ram FIFO in Xilinx, Ray Andraka
      • Re: Block-ram FIFO in Xilinx, Peter Alfke
      • Re: Block-ram FIFO in Xilinx, zlotawy
• USR_ACCESS_VIRTEX4 usage, Jan Pech
  • Re: USR_ACCESS_VIRTEX4 usage, Antti
    • Re: USR_ACCESS_VIRTEX4 usage, Jan Pech
• Xilinx ISE Timing Report Question, Peter Klemperer
  • Re: Xilinx ISE Timing Report Question, Jochen
    • Re: Xilinx ISE Timing Report Question, Peter Klemperer
• Xilinx Virtex-II Newbie, Andrew Ganger
  • Re: Xilinx Virtex-II Newbie, Andrew Ganger
    • Re: Xilinx Virtex-II Newbie, Andrew Ganger
      • Re: Xilinx Virtex-II Newbie, Nathan Bialke
      • Re: Xilinx Virtex-II Newbie, Andrew Ganger
      • Re: Xilinx Virtex-II Newbie, Nathan Bialke
      • Re: Xilinx Virtex-II Newbie, Nathan Bialke
      • Re: Xilinx Virtex-II Newbie, Peter Alfke
      • Re: Xilinx Virtex-II Newbie, Brian Drummond
      • Re: Xilinx Virtex-II Newbie, Andrew Ganger
      • Re: Xilinx Virtex-II Newbie, Brian Drummond
      • Re: Xilinx Virtex-II Newbie, Jim Granville
      • Re: Xilinx Virtex-II Newbie, Andrew Ganger
      • Re: Xilinx Virtex-II Newbie, EEngineer
      • Re: Xilinx Virtex-II Newbie, Jim Granville
    • Re: Xilinx Virtex-II Newbie, Andreas Ehliar
      • Re: Xilinx Virtex-II Newbie, Andrew Ganger
      • Re: Xilinx Virtex-II Newbie, Brian Drummond
      • Re: Xilinx Virtex-II Newbie, Andreas Ehliar
  • Re: Xilinx Virtex-II Newbie, EEngineer
    • Re: Xilinx Virtex-II Newbie, Andrew Ganger
      • Re: Xilinx Virtex-II Newbie, EEngineer
      • Re: Xilinx Virtex-II Newbie, EEngineer
      • Re: Xilinx Virtex-II Newbie, Andrew Ganger
      • Re: Xilinx Virtex-II Newbie, Jim Granville
      • Re: Xilinx Virtex-II Newbie, Andrew Ganger
      • Re: Xilinx Virtex-II Newbie, Jim Granville
      • Re: Xilinx Virtex-II Newbie, Andrew Ganger
• FPGA for hobby use, Herbert Kleebauer
  • Re: FPGA for hobby use, cs_posting
    • Re: FPGA for hobby use, Guenter Dannoritzer
    • Re: FPGA for hobby use, MikeShepherd564
      • Re: FPGA for hobby use, cs_posting
      • Re: FPGA for hobby use, Symon
      • Re: FPGA for hobby use, cs_posting
      • Re: FPGA for hobby use, Symon
      • Re: FPGA for hobby use, cs_posting
      • Re: FPGA for hobby use, Mike Treseler
      • Re: FPGA for hobby use, Symon
      • Re: FPGA for hobby use, Nial Stewart
      • Re: FPGA for hobby use, Ray Andraka
      • Re: FPGA for hobby use, cs_posting
      • Re: FPGA for hobby use, MikeShepherd564
    • Re: FPGA for hobby use, Herbert Kleebauer
    • Re: FPGA for hobby use, Andrew Burnside
  • Re: FPGA for hobby use, John Adair
  • Re: FPGA for hobby use, Jim Granville
    • Re: FPGA for hobby use, Herbert Kleebauer
      • Re: FPGA for hobby use, Andy
      • Re: FPGA for hobby use, Ray Andraka
      • Re: FPGA for hobby use, Dave
      • Re: FPGA for hobby use, Jonathan Bromley
      • Re: FPGA for hobby use, Ray Andraka
  • Re: FPGA for hobby use, Mike Treseler
    • Re: FPGA for hobby use, John Adair
  • Re: FPGA for hobby use, Brian Drummond
    • Re: FPGA for hobby use, Ray Andraka
      • Re: FPGA for hobby use, Brian Drummond
      • Re: FPGA for hobby use, Ray Andraka
  • Re: FPGA for hobby use, Nico Coesel
• Xilinx Encrypted bit file, Amal
  • Re: Xilinx Encrypted bit file, austin
    • Re: Xilinx Encrypted bit file, Symon
      • Re: Xilinx Encrypted bit file, austin
      • Re: Xilinx Encrypted bit file, Symon
      • Re: Xilinx Encrypted bit file, austin
      • Re: Xilinx Encrypted bit file, Matthieu
• grouping bits to form bus in VCD file, Heinrich Burgsteiner
• VCD Files Viewer?, Heinrich Burgsteiner
  • Re: VCD Files Viewer?, Jan Pech
    • Re: VCD Files Viewer?, Heinrich Burgsteiner
  • Re: VCD Files Viewer?, Guenter Dannoritzer
• REFCLK signal in Hard TEMAC core, JimboD2
• Synthesis-place&route performance test., posedge52
  • Re: Synthesis-place&route performance test., Jan Pech
  • Re: Synthesis-place&route performance test., Andreas Hofmann
• Chipscope Server for PowerPC?, biker
• [EDK simulation] synopsys translate_off, Pasacco
  • Re: synopsys translate_off, beeraka@xxxxxxxxx
    • Re: synopsys translate_off, Pasacco
      • Re: synopsys translate_off, Colin Paul Gloster
      • Re: synopsys translate_off, Pasacco
      • Re: synopsys translate_off, Pasacco
      • Re: synopsys translate_off, Duane Clark
      • Re: synopsys translate_off, beeraka@xxxxxxxxx
      • Re: synopsys translate_off, Pasacco
• how to make ports visible?, xenix
  • Re: how to make ports visible?, roger
• Structured way of changing eg time constants for real world build / simulation?, Nial Stewart
  • Re: Structured way of changing eg time constants for real world build / simulation?, Hal Murray
    • Re: Structured way of changing eg time constants for real world build / simulation?, Nial Stewart
  • Re: Structured way of changing eg time constants for real world build / simulation?, Brian Drummond
    • Re: Structured way of changing eg time constants for real world build / simulation?, Andy
      • Re: Structured way of changing eg time constants for real world build / simulation?, Nial Stewart
      • Re: Structured way of changing eg time constants for real world build / simulation?, Andy
      • Re: Structured way of changing eg time constants for real world build / simulation?, Andreas Ehliar
  • Re: Structured way of changing eg time constants for real world build / simulation?, John Adair
• implementing MAC protocols on fpga, dilip
  • Re: implementing MAC protocols on fpga, Stef
    • Re: implementing MAC protocols on fpga, dilip
      • Re: implementing MAC protocols on fpga, EEngineer
• bidirectional in fpga, fazulu deen
  • Re: bidirectional in fpga, mh
    • Re: bidirectional in fpga, MikeShepherd564
  • Re: bidirectional in fpga, Matthew Hicks
    • Re: bidirectional in fpga, fazulu deen
      • Re: bidirectional in fpga, commone
      • Re: bidirectional in fpga, Andy
• Asynchronous FIFO Latency., RaKa
  • Re: Asynchronous FIFO Latency., Peter Alfke
• DDR in spartan 3E, bhb
• Students: where to go for help, austin
  • Re: Students: where to go for help, Philip Potter
    • Re: Students: where to go for help, austin
      • Re: Students: where to go for help, Philip Potter
      • Re: Students: where to go for help, Symon
• Spartan3E Slave Serial Daisy chain, Andrew Greensted
  • Re: Spartan3E Slave Serial Daisy chain, Gabor
    • Re: Spartan3E Slave Serial Daisy chain, Andrew Greensted
  • Re: Spartan3E Slave Serial Daisy chain, John_H
  • Re: Spartan3E Slave Serial Daisy chain, Andrew Greensted
    • Re: Spartan3E Slave Serial Daisy chain, Gabor
      • Re: Spartan3E Slave Serial Daisy chain, Andrew Greensted
      • Re: Spartan3E Slave Serial Daisy chain, John_H
• Strange VHDL Error, Sascha Frank
  • Re: Strange VHDL Error, Sascha Frank
  • Re: Strange VHDL Error, Dave
    • Re: Strange VHDL Error, Sascha Frank
      • Re: Strange VHDL Error, HT-Lab
      • Re: Strange VHDL Error, Duane Clark
• EDK 8.2 tool : simulator set up, Pasacco
  • Re: EDK 8.2 tool : simulator set up, John McCaskill
    • Re: EDK 8.2 tool : simulator set up, Pasacco
• [EDK tool] simulation setup, Pasacco
  • Re: [EDK tool] simulation setup, Mike Treseler
• Programming connection, m
  • Re: Programming connection, m
  • Re: Programming connection, Petter Gustad
    • Re: Programming connection, Nial Stewart
      • Re: Programming connection, Petter Gustad
    • Re: Programming connection, m
  • Re: Programming connection, John_H
    • Re: Programming connection, m
      • Re: Programming connection, Gabor
• Xilinx USB cable in Fedora 7, Duane Clark
  • Re: Xilinx USB cable in Fedora 7, svenand
• newbie to 16v8, Amit
  • Re: newbie to 16v8, Jonathan Bromley
    • Re: newbie to 16v8, Amit
      • Re: newbie to 16v8, Peter Alfke
      • Re: newbie to 16v8, General Schvantzkoph
  • Re: newbie to 16v8, Jim Granville
  • Re: newbie to 16v8, David Spencer
    • Re: newbie to 16v8, Jim Granville
    • Re: newbie to 16v8, Nico Coesel
      • Re: newbie to 16v8, Peter Alfke
      • Re: newbie to 16v8, David Spencer
      • Re: newbie to 16v8, Jim Granville
      • Re: newbie to 16v8, David Spencer
      • Re: newbie to 16v8, Jim Granville
  • Re: newbie to 16v8, Ray Andraka
    • Re: newbie to 16v8, Amit
      • Re: newbie to 16v8, Brian Drummond
      • Re: newbie to 16v8, BobW
      • Re: newbie to 16v8, Amit
      • Re: newbie to 16v8, Ray Andraka
• 7000+ beautiful Russian women, my god
• Is "Insight IJC-02" and "Xilinx parallel download cable" the same?, kgll8ss
• SystemACE generation, ajith.thamara@xxxxxxxxx
• System ACE generation, ajith.thamara@xxxxxxxxx
• Bitslip function in the V5 GTP Transmitter, cpandya
• What the 'c2p' and 'c2o' stand for?, ZHI
  • Re: What the 'c2p' and 'c2o' stand for?, John_H
• ROM (altsyncram) corruption, cs_posting
  • Re: ROM (altsyncram) corruption, MikeShepherd564
    • Re: ROM (altsyncram) corruption, cs_posting
      • Re: ROM (altsyncram) corruption, Symon
      • Re: ROM (altsyncram) corruption, Peter Alfke
      • Re: ROM (altsyncram) corruption, cs_posting
      • Re: ROM (altsyncram) corruption, Eric Smith
      • Re: ROM (altsyncram) corruption, Peter Alfke
      • Re: ROM (altsyncram) corruption, Peter Alfke
      • Re: ROM (altsyncram) corruption, Allan Herriman
      • Re: ROM (altsyncram) corruption, Peter Alfke
      • Re: ROM (altsyncram) corruption, Allan Herriman
• EDK 9.2 install problem, Philip Potter
  • Re: EDK 9.2 install problem, Philip Potter
    • Re: EDK 9.2 install problem, Andreas Hofmann
• IAR Embedded Workbench, Zuken Cadstar, Proteus, Altium Designer, Xilinx.EDK.v9.1, Xilinx PlanAhead, Xilinx ChipScope Pro, Cadence OrCAD, Agilent Genesys, MENTOR.GRAPHICS.MODELSIM, other ..., ola
• is marked OBSOLETE????, xenix
  • Re: is marked OBSOLETE????, Jon Beniston
• MANIK LwIP port, Ju, Jian
• Xilinx Parallel Cable IV, API spec, kgll8ss
  • Re: Xilinx Parallel Cable IV, API spec, kgll8ss
  • Re: Xilinx Parallel Cable IV, API spec, Antti
    • Re: Xilinx Parallel Cable IV, API spec, kgll8ss
      • Re: Xilinx Parallel Cable IV, API spec, cs_posting
      • Re: Xilinx Parallel Cable IV, API spec, Eric Smith
      • Re: Xilinx Parallel Cable IV, API spec, Antti
      • Re: Xilinx Parallel Cable IV, API spec, cs_posting
      • Re: Xilinx Parallel Cable IV, API spec, Eric Smith
      • Re: Xilinx Parallel Cable IV, API spec, cs_posting
      • Re: Xilinx Parallel Cable IV, API spec, Antti
• Microblaze PLB vs. OPB busses, Eric Smith
  • Re: Microblaze PLB vs. OPB busses, Jeff Cunningham
• Spartan 3E Starter Kit DDR RAM, maxbatley
  • Re: Spartan 3E Starter Kit DDR RAM, Tommy Thorn
• Spartan 3E config, maxascent
  • Re: Spartan 3E config, Bryan
• Maximum current drive according to datasheet ?!, jidan1
  • Re: Maximum current drive according to datasheet ?!, RCIngham
    • Re: Maximum current drive according to datasheet ?!, jidan1
      • Re: Maximum current drive according to datasheet ?!, austin
      • Re: Maximum current drive according to datasheet ?!, jidan1
      • Re: Maximum current drive according to datasheet ?!, Jim Granville
      • Re: Maximum current drive according to datasheet ?!, John_H
      • Re: Maximum current drive according to datasheet ?!, John_H
  • Re: Maximum current drive according to datasheet ?!, austin
• FIFO interface design, Readon
  • Message not available
    • Re: FIFO interface design, Readon
      • Re: FIFO interface design, Gabor
      • Re: FIFO interface design, John Retta
      • Re: FIFO interface design, Readon
      • Re: FIFO interface design, John Retta
      • Re: FIFO interface design, John_H
      • Re: FIFO interface design, Marlboro
• P160 Communication Module 3, ratemonotonic
  • Re: P160 Communication Module 3, Sean Durkin
    • Re: P160 Communication Module 3, ratemonotonic
      • Re: P160 Communication Module 3, Sean Durkin
      • Re: P160 Communication Module 3, Bryan
      • Re: P160 Communication Module 3, ratemonotonic
• Non-volatile FPGA in a small package, rickman
  • Re: Non-volatile FPGA in a small package, Symon
  • Re: Non-volatile FPGA in a small package, Jim Granville
  • Re: Non-volatile FPGA in a small package, Marc A. Baker
    • Re: Non-volatile FPGA in a small package, rickman
      • Re: Non-volatile FPGA in a small package, Brian Drummond
      • Re: Non-volatile FPGA in a small package, rickman
    • Re: Non-volatile FPGA in a small package, Uwe Bonnes
  • Re: Non-volatile FPGA in a small package, Alex
    • Re: Non-volatile FPGA in a small package, rickman
      • Re: Non-volatile FPGA in a small package, Maki
      • Re: Non-volatile FPGA in a small package, Alex
      • Re: Non-volatile FPGA in a small package, rickman
      • Re: Non-volatile FPGA in a small package, Maki
      • Re: Non-volatile FPGA in a small package, Gabor
      • Re: Non-volatile FPGA in a small package, lb . edc
  • Re: Non-volatile FPGA in a small package, Kryvor
    • Re: Non-volatile FPGA in a small package, John_H
      • Re: Non-volatile FPGA in a small package, Kris Vorwerk
    • Re: Non-volatile FPGA in a small package, cs_posting
      • Re: Non-volatile FPGA in a small package, Thomas Stanka
      • Re: Non-volatile FPGA in a small package, cs_posting
      • Re: Non-volatile FPGA in a small package, Kris Vorwerk
• Custom processor developement issues, argee
  • Re: Custom processor developement issues, Andrew FPGA
    • Re: Custom processor developement issues, argee
      • Re: Custom processor developement issues, austin
  • Re: Custom processor developement issues, KJ
    • Re: Custom processor developement issues, KJ
  • Re: Custom processor developement issues, argee
• did i miss edk 9.2, u_stadler@xxxxxxxx
  • Re: did i miss edk 9.2, MM
    • Re: did i miss edk 9.2, Alain
      • Re: did i miss edk 9.2, svenand
      • Re: did i miss edk 9.2, satih82
      • Re: did i miss edk 9.2, Ken Ryan
• [Linker script : EDK6.3 -> EDK 8.2] Parse error, Pasacco
  • Re: [Linker script : EDK6.3 -> EDK 8.2] Parse error, Minh Nguyen
• FPGA Clock signal, raullim7
  • Re: FPGA Clock signal, roger
  • Re: FPGA Clock signal, John_H
    • Re: FPGA Clock signal, raullim7
      • Re: FPGA Clock signal, John LeVieux
      • Re: FPGA Clock signal, Naive_Algorithm
• Time Delay in FPGA, raullim7
  • Re: Time Delay in FPGA, roger
• Re: not totally repulsive, Symon
  • Re: not totally repulsive, BobW
  • Re: not totally repulsive, Jim Granville
  • <Possible follow-ups>
  • Re: not totally repulsive, Symon
  • Re: not totally repulsive, MikeShepherd564
• Re: Fast Sampling of digital signals, fpgauser
• Why dynamic partial reconfiguration is still not there?, psihodelia@xxxxxxxxxxxxxx
  • Re: Why dynamic partial reconfiguration is still not there?, Mike Treseler
    • Re: Why dynamic partial reconfiguration is still not there?, Adam Megacz
      • Re: Why dynamic partial reconfiguration is still not there?, Mike Treseler
  • Re: Why dynamic partial reconfiguration is still not there?, fpgauser
• ERROR:MDT - transparent bus interface connector, xenix
  • Re: ERROR:MDT - transparent bus interface connector, morphiend
    • Re: ERROR:MDT - transparent bus interface connector, xenix
• May i program a Spartan 3 fpga with a 1,8 V Digilent cable?, blisca
  • Re: May i program a Spartan 3 fpga with a 1,8 V Digilent cable?, Gabor
    • R: May i program a Spartan 3 fpga with a 1,8 V Digilent cable?, blisca
• Re: Linux capable free/GPL SOFT CPU for XC3S500E?, mares . vit
  • Re: Linux capable free/GPL SOFT CPU for XC3S500E?, Wojciech Zabolotny
    • Re: Linux capable free/GPL SOFT CPU for XC3S500E?, mares . vit
      • Re: Linux capable free/GPL SOFT CPU for XC3S500E?, Wojciech Zabolotny
      • Re: Linux capable free/GPL SOFT CPU for XC3S500E?, mares . vit
  • <Possible follow-ups>
  • Re: Linux capable free/GPL SOFT CPU for XC3S500E?, Steven Derrien
  • Re: Linux capable free/GPL SOFT CPU for XC3S500E?, Andreas Ehliar
  • Re: Linux capable free/GPL SOFT CPU for XC3S500E?, Wojciech Zabolotny
• Re: Is it possible to debug a vhdl design over jtag?, Pablo
• FPGA I/O Selection in UCF, jtindle
  • Re: FPGA I/O Selection in UCF, Gabor
    • Re: FPGA I/O Selection in UCF, jtindle
      • Re: FPGA I/O Selection in UCF, austin
      • Re: FPGA I/O Selection in UCF, Hal Murray
  • Re: FPGA I/O Selection in UCF, morphiend
  • Re: FPGA I/O Selection in UCF, austin
    • Re: FPGA I/O Selection in UCF, jtindle
• Re: Weird behavior : Altera DE2, C++, For loops, SRAM, prof . brown
• linking error using mb-g++, Bathala
• Global Variables, raullim7
  • Re: Global Variables, RCIngham
    • Re: Global Variables, Andy
• Linux (not uClinux) on Microblaze 7.0 w/MMU?, Eric Smith
  • Re: Linux (not uClinux) on Microblaze 7.0 w/MMU?, morphiend
• Audio Output from Spartan 3 Starter Kit, Bryan
  • Re: Audio Output from Spartan 3 Starter Kit, MikeShepherd564
    • Re: Audio Output from Spartan 3 Starter Kit, Ray Andraka
      • Re: Audio Output from Spartan 3 Starter Kit, MikeShepherd564
      • Re: Audio Output from Spartan 3 Starter Kit, Peter Alfke
• DDR2 Interface, maxascent
  • Re: DDR2 Interface, austin
• APU (xilinx PPC) is it a soft core ?, me_2003
  • Re: APU (xilinx PPC) is it a soft core ?, austin
• Xilinx PCI-express coregen, water9580@xxxxxxxxx
  • Re: Xilinx PCI-express coregen, John_H
• Xilinx PCI-Express Endpoint Block IP, water9580@xxxxxxxxx
  • Re: Xilinx PCI-Express Endpoint Block IP, sovan
    • Re: Xilinx PCI-Express Endpoint Block IP, water9580@xxxxxxxxx
• Re: Power supply filter capacitors, Nevo
• Static PLL, Vince
  • Re: Static PLL, MikeShepherd564
    • Re: Static PLL, rouzbeh . h
      • Re: Static PLL, Vince
      • Re: Static PLL, rouzbeh . h
• Problem using xilinx usb download cable in linux, roger
  • Re: Problem using xilinx usb download cable in linux, Michael Gernoth
    • Re: Problem using xilinx usb download cable in linux, roger
    • Re: Problem using xilinx usb download cable in linux, roger
      • Re: Problem using xilinx usb download cable in linux, Michael Gernoth
      • Re: Problem using xilinx usb download cable in linux, Ken Ryan
• How do I meet this memory IO with least resources on FPGA?, G Iveco
  • Re: How do I meet this memory IO with least resources on FPGA?, KJ
    • Re: How do I meet this memory IO with least resources on FPGA?, G Iveco
      • Re: How do I meet this memory IO with least resources on FPGA?, KJ
  • Re: How do I meet this memory IO with least resources on FPGA?, Nico Coesel
    • Re: How do I meet this memory IO with least resources on FPGA?, Peter Alfke
      • Re: How do I meet this memory IO with least resources on FPGA?, G Iveco
      • Re: How do I meet this memory IO with least resources on FPGA?, Peter Alfke
  • Re: How do I meet this memory IO with least resources on FPGA?, evilkidder@xxxxxxxxxxxxxx
  • Re: How do I meet this memory IO with least resources on FPGA?, Alvin Andries
• Synthesizing with specific primitive-elements, giorgos . puiklis
  • Re: Synthesizing with specific primitive-elements, mk
  • Re: Synthesizing with specific primitive-elements, John_H
  • Re: Synthesizing with specific primitive-elements, comp.arch.fpga
• Spartan-3 (XC3S400) DDR LVDS support?, kgll8ss
  • Re: Spartan-3 (XC3S400) DDR LVDS support?, lb . edc
• Xilinx EDK and Windows Vista?, Xilinx User
  • Re: Xilinx EDK and Windows Vista?, ghelbig
    • Re: Xilinx EDK and Windows Vista?, steve.lass
      • Re: Xilinx EDK and Windows Vista?, Dave
      • Re: Xilinx EDK and Windows Vista?, steve.lass
• code hang after loading through gdb, xmkong
  • Re: code hang after loading through gdb, morphiend
    • Re: code hang after loading through gdb, xmkong
      • Re: code hang after loading through gdb, xmkong
• Re: debugging ppc + mb, me_2003
  • Re: debugging ppc + mb, John Williams
• To Xilinx users - PLB bus features (for PPC), me_2003
  • Re: To Xilinx users - PLB bus features (for PPC), slmccaskill
• Xilinx's System Generator versus Mathworks' Link for Modelsim, brianwfarmer
  • Re: Xilinx's System Generator versus Mathworks' Link for Modelsim, Mike Treseler
• fpga based designs, fazulu deen
  • Re: fpga based designs, John_H
  • Re: fpga based designs, John McCaskill
    • Re: fpga based designs, vasile
  • Re: fpga based designs, Kris Vorwerk
• Another way to handle floating inputs., Petrov_101
  • Re: Another way to handle floating inputs., austin
    • Re: Another way to handle floating inputs., Petrov_101
      • Message not available
      • Re: Another way to handle floating inputs., Petrov_101
      • Re: Another way to handle floating inputs., austin
  • Re: Another way to handle floating inputs., Jim Granville
    • Re: Another way to handle floating inputs., Petrov_101
  • Re: Another way to handle floating inputs., Peter Alfke
    • Re: Another way to handle floating inputs., RCIngham
      • Re: Another way to handle floating inputs., Peter Alfke
      • Re: Another way to handle floating inputs., RCIngham
  • Re: Another way to handle floating inputs., comp.arch.fpga
    • Re: Another way to handle floating inputs., Peter Alfke
      • Re: Another way to handle floating inputs., Jim Granville
      • Re: Another way to handle floating inputs., Peter Alfke
      • Re: Another way to handle floating inputs., Peter Alfke
• ISE ignores LOC constraints for BUFGMUX clock buffers, noreply . larthe
  • Re: ISE ignores LOC constraints for BUFGMUX clock buffers, noreply . larthe
• Re: HELP, how to time constraint part of a design?, Brian Drummond
• Re: 2 FPGAs /w programming FLASH in one JTAG chain, Toni Merwec
  • Re: 2 FPGAs /w programming FLASH in one JTAG chain, colin
    • Re: 2 FPGAs /w programming FLASH in one JTAG chain, Toni Merwec
• Re: xilinx bmm file problem, Arnim
  • <Possible follow-ups>
  • Re: xilinx bmm file problem, taco
• can i use dual edge or two clocks?, raullim7
  • Re: can i use dual edge or two clocks?, Frank Buss
    • Re: can i use dual edge or two clocks?, David R Brooks
    • Re: can i use dual edge or two clocks?, raullim7
      • Re: can i use dual edge or two clocks?, Mike Lewis
      • Re: can i use dual edge or two clocks?, Peter Alfke
      • Re: can i use dual edge or two clocks?, Mike Lewis
      • Re: can i use dual edge or two clocks?, Matthew Hicks
      • Re: can i use dual edge or two clocks?, Jim Granville
      • Re: can i use dual edge or two clocks?, Symon
      • Re: can i use dual edge or two clocks?, Jim Granville
      • Re: can i use dual edge or two clocks?, raullim7
      • Re: can i use dual edge or two clocks?, Thomas Stanka
      • Re: can i use dual edge or two clocks?, raullim7
      • Re: can i use dual edge or two clocks?, Frank Buss
  • Re: can i use dual edge or two clocks?, MM
• Re: IDE to Flash memory, Franck
• Re: FPGA vs ASIC, mk
  • Re: FPGA vs ASIC, Peter Alfke
    • Re: FPGA vs ASIC, mk
  • Re: FPGA vs ASIC, John_H
  • <Possible follow-ups>
  • Re: FPGA vs ASIC, glen herrmannsfeldt
    • Re: FPGA vs ASIC, Ray Andraka
      • Re: FPGA vs ASIC, Peter Alfke
• Re: Capability of a FPGA device., evilkidder@xxxxxxxxxxxxxx
  • <Possible follow-ups>
  • Re: Capability of a FPGA device., MMJ
  • Re: Capability of a FPGA device., csantos
    • Re: Capability of a FPGA device., MMJ
      • Re: Capability of a FPGA device., Kris Vorwerk
• Re: Ping Jim: The PFD is dead!, Symon
  • Re: Ping Jim: The PFD is dead!, Peter Alfke
• Digilent V2P Board, David Binnie
  • Re: Digilent V2P Board, Andreas Ehliar

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newsgroups.derkeiler.com  > Archive  > Comp  > comp.arch.fpga  > 2007-11