Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?

"Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote in
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I would never split a plane except as a last resort (unless you can
sandwich it between two solid planes - I often use a four layer GND,
split power, split power, GND sandwich in the middle of 16-20 layer
boards), because of the issues with traces crossing the split.

As you say below signals can use the PWR plane as a 'pseudo gnd'.

By using this stack are you not loosing the ability to route two internal
signal layers adjacent to the GND planes, and the additional use of the
PWR planes as pseudo grounds?

Nial.

No, because everything is referenced to ground. My favorite stackups are:

12-layer S, G, S, S, G, P, P, G, S, S, G, S
14-layer microvia S, S, G, S, S, G, P, P, G, S, S, G, S, S
18-layer S, G, S, S, G, S, S, G, P, P, G, S, S, G, S, S, G, S
20-layer microvia S, S, G, S, S, G, S, S, G, P, P, G, S, S, G, S, S, G,
S, S

S = Signal, G = Ground, P = Power.
Microvias are laser-drilled vias going from the outside down just one
layer - makes double-sided fan-out on high density boards much easier.

The advantages of these stackups are:
1. All signal layers are referenced to a real ground plane.
2. For normal board thicknesses (1.6 - 2.5 mm) it is easy to get 50-ohm
single-ended and 100-ohm differential impedance on the inner signal layers
with 4 mil track and gap (the outers give you about 42 ohms with 5 mil
traces).
3. You can use ZBC cores on the innermost power stack up achieve buried
capacitance decoupling.
4. You can split the power planes as much as you like without having to
worry about signal integrity, because the splits are caged.
5. You can adjust the thickness of the board by changing the prepreg between
the two power layers without having any real effect on the electrical
characteristics.

The possible disadvantages are:
1. The via length down to the power planes will be longer than had the
planes been closer to the surface, but this is unlikely to cause a problem.
2. The board cost in increased somewhat over a six or eight layer one, but
not by as much as you might think.


.

Relevant Pages

  • Re: Power Planes and Bypass Capacitors
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    (sci.electronics.design)
  • Re: Power Planes and Bypass Capacitors
    ... Three of the layers will be for power planes which will have +5V, gnd, and -5V. ... This will make the power planes a large capacitor throughout board. ... The component surface layer and the layer just under it are for routing. ...
    (sci.electronics.design)
  • Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
    ... planes - I often use a four layer GND, split power, split power, GND sandwich in the middle of ... 16-20 layer boards), because of the issues with traces crossing the split. ... signal layers adjacent to the GND planes, and the additional use of the ...
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