Re: How do I meet this memory IO with least resources on FPGA?
- From: "KJ" <kkjennings@xxxxxxxxxxxxx>
- Date: Sat, 03 Nov 2007 20:25:56 GMT
"G Iveco" <G.Iveco@xxxxxxxxxx> wrote in message
news:fgibec$2b5$1@xxxxxxxxxxxxxxxxxxxxxxxxxx
But it really doesn't matter. When you follow the proper template, your
But my question is, for memory based systems,
For very large memory, register implementation takes N times silicon than
RAM.
For a small memory, RAM have overheads like RW, sensing, amplifier, etc
which may
be equivalent to a few hundred registers in terms of silicon and power.
as a result, in the 2nd case, how much is this RAM overhead comparing to a
32-bit register in
Xilinx?
code can be synthesized to use internal RAM or LUTs. That decision will be
made by the synthesis tool. So look up the form of VHDL that will infer
memory, write your code in that fashion, avoid use of wizards and such, and
your code will synthesize to fit into the resources that are on the chip.
It makes no difference whether the memory gets implemented in logic cells or
memory arrays as long as it
- implements the intended function
- meets the performance requirements
- Fits in the targetted device.
If there are good comparisons, then I can skip the trouble of testing..Testing which 'method' is better is pointless. Write code that can be
inferred properly to the targetted part and leave the rest for the tools to
implement.
KJ
.
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