Re: Is it possible to check how cache memories are mapped to FPGA block rams?

Wei Wang wrote:
Eric, I appreciate your willingness to dig further to help, but my
question was how I could check the block ram mapping of my design
which I thought it was quite generic, and I would expect answers, such

Without looking at your HDL code, I don't think we have any clue how
you've attached the blockrams to your CPU, so I'm not sure how we
could tell you how to check the mapping.

BTW, I
suppose most of us in this group do not work for ourselves, only lazy
university students would post their entire project and let somebody
else do the work for them.

In general, I agree. But sometimes it's hard to offer any help without
more detail, and sometimes the easiest way to see the relevant detail
is to look at the HDL.

I'm sorry that I don't have any more specific advice to offer.

Best regards,
Eric

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