Re: Xilinx, MIG, UCF: timing constraints for DDR2 DRAM
- From: "Simon Heinzle" <sheinzle@xxxxxxxxxxx>
- Date: Tue, 30 Oct 2007 17:41:48 +0100
Hi all,
I found the problem: the "Retiming" option in Synplify Pro caused the
address signals to be retimed and they could therefore not be packed into an
IOB flip flop. This caused a much higher delay than in the other output
signals.
Thanks for your help,
Simon
"Simon Heinzle" <sheinzle@xxxxxxxxxxx> wrote in message
news:47261129$1@xxxxxxxxxxxxxxxxxxxxxx
Hi FPGA Group!
I'm struggling to get a fast speed (~ 200 MHz) for the DDR2 DRAM
interface, generated with the Xilinx Memory Interface Generator. The
complete system consists of a PCI interface, an I/O DMA buffer, a burst
module bursting from DMA buffer to the DDR2 DRAM interface.
What is the best way to define setup/hold times for the I/O pads (UCF)?
(the RAM interface consists of a bi-dir data bus DQ, some output signals
e.g. A and the DRAM clocks CK)
1. Using the OFFSET = OUT 5 ns AFTER "SYS_CLK_P"? Unfortunately, this does
only work using the Input Clock Pin, but it should probably better be in
reference to the DRAM clocks CK)
2. Using TIMESPEC "TS_DDR_OUT" = FROM FFS TO "DDR_OUT" 5 ns; ? Is probably
better, but I'm not exactly sure.
Furthermore, how would you tackle the problem if the timing at the pads
cannot be met?
Thanks in advance for helpful answers and pointers in the right direction!
Best regards,
Simon
.
- References:
- Xilinx, MIG, UCF: timing constraints for DDR2 DRAM
- From: Simon Heinzle
- Xilinx, MIG, UCF: timing constraints for DDR2 DRAM
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