Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround

On Oct 17, 4:19 pm, Antti <Antti.Luk...@xxxxxxxxxxxxxx> wrote:
On 17 Okt., 23:15, Dave <dhsch...@xxxxxxxxx> wrote:



Antti,

Could you fix the typo on the line with the do64(62 downto 0)
assignment - there's an array length mismatch. Also, what is the
definition of do64 - std_logic_vector(63 downto 0)?

On Oct 17, 4:44 pm, Antti <Antti.Luk...@xxxxxxxxxxxxxx> wrote:

Hi ho

here is code

process (m_sck) begin
if (m_sck'event and m_sck='1') then
do64(62 downto 0) <= do64(62 downto 0) & M_DI;
end if;
end process;
LEDS <= do64s(63 downto 60);

M_DI, M_SCK are driven by external MCU SPI interface.
the MCU send either
0x90 00 00 00 00 00 00 00
or
0x00 00 00 00 00 00 00 00

symptoms: when FPGA is not full, the LED blink, all OFF, 1-0-0-1
when the FPGA is full, there will blink all off, then 1-1-0-1
repeating same pattern, not randomness

changing maxfanout in synplify will change the erratic behaviour but I
have not managed to get the shift register ever work in case where
FPGA is really full.

SPI clock is 4MHz (or lower doesn seem to make any difference)

this time I am giving up, that is not trying to force the shift
register to work, but find solution that works

the problem only occourcs on Actel FPGA, and yes yes it works in
símulation it works in xilinx FPGA, etc..

Antti
who this time really doesnt know the solution :(- Zitierten Text ausblenden -

- Zitierten Text anzeigen -

sorry my eyes see double(almost, just hurt), i cleaned the code and
madetypo

signal do64 : std_logic_vector(63 downto 0) ;

process (m_sck) begin
if (m_sck'event and m_sck='1') then
do64(63 downto 0) <= do64(62 downto 0) & M_DI;
end if;
end process;
LEDS <= do64(63 downto 60);

The code seems pretty straight forward. One question though: are you
expecting the groups of four output bits to line up on some magical
boundary? If so, you'd obviously need a sync or reset pulse.

Ignoring the four bit alignment, is m_sck landing on the dedicated
clocking resources of the Actel part? If so, I'm guessing your
problem has nothing to do with the the shift register code. What is
the toggle rates of m_sck compared to M_DI, and just as important, the
clock to data alignment between the two? Have you brought m_sclk out
an I/O pin to verify its frequency and phase relationship with M_DI?
Brought M_DI back out an I/O pin after being sampled by m_sck to
verify that it's being sampled correctly?

Have fun,

Marc

.

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