Re: 2 leg crystal on FPGA: Lattice vs Xilinx

On 1 Okt., 19:56, Jon Elson <el...@xxxxxxxxx> wrote:
Antti wrote:
Hi

I know many wise men has said NO NO, but

1)
http://www.latticesemi.com/forums/forum/messageview.cfm?catid=42&thre...

Lattice engineer suggest that it works (assumable reliable) on machXO

the IO technology between machXO and Xilinx FPGAs isnt so big so I
wonder why cant it be done with Xilinx ?

for what I see is following

25MHz crystal
27p caps
560 series
1M parallel

when using LVCMOS33 SLEW=FAST

I can't address the specific chip, and you have to think about
input->output delay, but it shouldn't be a big problem. I did just this
on a recent design using a Xilinx 5V CPLD, and it worked beautifully
with a 10 MHz crystal. I used no parallel resistor, and no series
resistor, although I was just a little worried about overdrive, there.
My caps were 15 pF (xtal vendor recommended 18 pF, but I have some
parasitic capacitance on the board and chip pins). As far as I can tell
it is working like a dream.

You might set the slew to slow, that is still plenty fast for a 25 MHz
signal.

Jon- Zitierten Text ausblenden -

- Zitierten Text anzeigen -

well, its not "might" in some cases you "need" set slew slow (or maybe
further adjust the component values)
with slew-fast on S3A there was overdrive overkilling the oscillation
so it periodically stopped and started again
(the inverter output only, the input was always seeing the crystal
swing), but the DC bias did run away into
outside the input range so the internal signal did stop.

well, maybe have to use "safe ring oscillator" to bootstrap and
monitor the crystal circuit and DCM locks
but I think with extreme care and bench testing it should be all
doable

Antti




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