comp.arch.fpga

• Date Index

---

• Spartan-3E display developpement kit, bhb
• Capability of a FPGA device., MMJ
  • Re: Capability of a FPGA device., Antti
  • Re: Capability of a FPGA device., John_H
  • Re: Capability of a FPGA device., Jim Granville
• xilinx bmm file problem, taco
  • Re: xilinx bmm file problem, Antti
• ERROR:Simulator:222 - Generated C++ compilation was unsuccessful, ogrenci
• Is it possible to debug a vhdl design over jtag?, Pablo
  • Re: Is it possible to debug a vhdl design over jtag?, Antti
  • Re: Is it possible to debug a vhdl design over jtag?, comp.arch.fpga
    • Re: Is it possible to debug a vhdl design over jtag?, morphiend
      • Re: Is it possible to debug a vhdl design over jtag?, Andy
  • Re: Is it possible to debug a vhdl design over jtag?, MM
    • Re: Is it possible to debug a vhdl design over jtag?, Mike Treseler
• Weird behavior : Altera DE2, C++, For loops, SRAM, sendthis
• debugging ppc + mb, me_2003
  • Re: debugging ppc + mb, Vasanth Asokan
  • Re: debugging ppc + mb, John Williams
• Updating my bookshelf, Nicolas Matringe
  • Re: Updating my bookshelf : looking for recommendations, Nicolas Matringe
  • Re: Updating my bookshelf, Mike Treseler
    • Re: Updating my bookshelf, Gabor
  • Re: Updating my bookshelf, RCIngham
• X3100A design with Synplify 8.8 and foundation 1.5 possible?, Antti
  • Message not available
    • Re: X3100A design with Synplify 8.8 and foundation 1.5 possible?, Antti
• IDE to Flash memory, Franck
  • Re: IDE to Flash memory, Antti
    • Re: IDE to Flash memory, Franck
      • Re: IDE to Flash memory, Antti
• FFT for an arbitrary number of points (not power of 2), Patrick Dubois
  • Re: FFT for an arbitrary number of points (not power of 2), Andy Botterill
    • Re: FFT for an arbitrary number of points (not power of 2), Patrick Dubois
  • Re: FFT for an arbitrary number of points (not power of 2), RCIngham
  • Re: FFT for an arbitrary number of points (not power of 2), RCIngham
    • Re: FFT for an arbitrary number of points (not power of 2), Patrick Dubois
  • Re: FFT for an arbitrary number of points (not power of 2), John_H
    • Re: FFT for an arbitrary number of points (not power of 2), Patrick Dubois
      • Re: FFT for an arbitrary number of points (not power of 2), dbd
      • Re: FFT for an arbitrary number of points (not power of 2), Patrick Dubois
  • Re: FFT for an arbitrary number of points (not power of 2), John McCaskill
  • Re: FFT for an arbitrary number of points (not power of 2), Andrew FPGA
  • Re: FFT for an arbitrary number of points (not power of 2), Ray Andraka
    • Re: FFT for an arbitrary number of points (not power of 2), Patrick Dubois
• Xilinx, MIG, UCF: timing constraints for DDR2 DRAM, Simon Heinzle
  • Re: Xilinx, MIG, UCF: timing constraints for DDR2 DRAM, Eric Crabill
    • Re: Xilinx, MIG, UCF: timing constraints for DDR2 DRAM, Simon Heinzle
  • Re: Xilinx, MIG, UCF: timing constraints for DDR2 DRAM, Simon Heinzle
• registers are not shown in waveform (xilinx microblaze), dartanian
  • Re: registers are not shown in waveform (xilinx microblaze), Mike Treseler
  • Re: registers are not shown in waveform (xilinx microblaze), Göran Bilski
• Re: 3 input adder in Spartan 3E, MGT78000
• Is it possible to check how cache memories are mapped to FPGA block rams?, Wei Wang
  • Re: Is it possible to check how cache memories are mapped to FPGA block rams?, Antti
  • Re: Is it possible to check how cache memories are mapped to FPGA block rams?, Eric Smith
    • Re: Is it possible to check how cache memories are mapped to FPGA block rams?, Wei Wang
      • Re: Is it possible to check how cache memories are mapped to FPGA block rams?, morphiend
      • Re: Is it possible to check how cache memories are mapped to FPGA block rams?, Eric Smith
      • Re: Is it possible to check how cache memories are mapped to FPGA block rams?, Mike Lewis
    • Re: Is it possible to check how cache memories are mapped to FPGA block rams?, HT-Lab
• 2 FPGAs /w programming FLASH in one JTAG chain, Toni Merwec
  • Re: 2 FPGAs /w programming FLASH in one JTAG chain, Patrick Dubois
  • Re: 2 FPGAs /w programming FLASH in one JTAG chain, Uwe Bonnes
  • Re: 2 FPGAs /w programming FLASH in one JTAG chain, David Spencer
• How to make sure processor memories have been correctly mapped onto block ram on fpga?, Wei Wang
• FPGA Configuration, vlsi_freak
  • Re: FPGA Configuration, Antti
    • Re: FPGA Configuration, Thomas Stanka
      • Re: FPGA Configuration, Antti
  • Re: FPGA Configuration, MikeShepherd564
    • Re: FPGA Configuration, Peter Alfke
      • Re: FPGA Configuration, MikeShepherd564
      • Re: FPGA Configuration, Peter Alfke
    • Re: FPGA Configuration, Symon
      • Re: FPGA Configuration, John_H
      • Re: FPGA Configuration, KJ
      • Re: FPGA Configuration, Andy
• Final CFP: 2008 International Workshop on Multi-Core Computing Systems, Sabri . Pllana
• Xilinx xflow for the ISE Quickstart Tutorial project?, Bob Smith
  • Re: Xilinx xflow for the ISE Quickstart Tutorial project?, John Retta
    • Re: Xilinx xflow for the ISE Quickstart Tutorial project?, Bob Smith
      • Re: Xilinx xflow for the ISE Quickstart Tutorial project?, John Retta
• HPCNCS-08 Call for papers, john
• total equivalent gate count, nagaraj
  • Re: total equivalent gate count, austin
• Selecting I/O pins, Ved
  • Re: Selecting I/O pins, John Retta
  • Re: Selecting I/O pins, David Spencer
• Bitfile checking, Walters
  • Re: Bitfile checking, Antti
    • Re: Bitfile checking, MikeShepherd564
    • Re: Bitfile checking, Ed McGettigan
      • Re: Bitfile checking, Antti
      • Re: Bitfile checking, Ed McGettigan
      • Re: Bitfile checking, Antti
• How to use an internal signal in a testbench..., motty
  • Re: How to use an internal signal in a testbench..., Jonathan Bromley
    • Re: How to use an internal signal in a testbench..., motty
      • Re: How to use an internal signal in a testbench..., Jonathan Bromley
• Xilinx Isolate circuitry, Berk Birand
  • Re: Xilinx Isolate circuitry, David Spencer
  • Re: Xilinx Isolate circuitry, KJ
  • Re: Xilinx Isolate circuitry, Symon
  • Re: Xilinx Isolate circuitry, Brian Drummond
• XMD with CableServer OR remote EDK solution, Patrick Dubois
  • Re: XMD with CableServer OR remote EDK solution, Antti
    • Re: XMD with CableServer OR remote EDK solution, Patrick Dubois
      • Re: XMD with CableServer OR remote EDK solution, Petter Gustad
      • Re: XMD with CableServer OR remote EDK solution, Antti
• FPGA vs ASIC, fpgabuilder
  • Re: FPGA vs ASIC, Jonathan Bromley
    • Re: FPGA vs ASIC, Ray Andraka
      • Re: FPGA vs ASIC, John_H
      • Re: FPGA vs ASIC, Andrew FPGA
      • Re: FPGA vs ASIC, Philip Potter
      • Re: FPGA vs ASIC, mk
      • Re: FPGA vs ASIC, Andy
      • Re: FPGA vs ASIC, mk
      • Re: FPGA vs ASIC, Thomas Stanka
      • Re: FPGA vs ASIC, mk
      • Re: FPGA vs ASIC, Andrew FPGA
      • Re: FPGA vs ASIC, Philip Potter
      • Re: FPGA vs ASIC, glen herrmannsfeldt
    • Re: FPGA vs ASIC, fpgabuilder
      • Re: FPGA vs ASIC, Jonathan Bromley
  • Re: FPGA vs ASIC, Jecel
  • Re: FPGA vs ASIC, Thomas Stanka
    • Re: FPGA vs ASIC, mk
      • Re: FPGA vs ASIC, Thomas Stanka
      • Re: FPGA vs ASIC, mk
      • Re: FPGA vs ASIC, Thomas Stanka
      • Re: FPGA vs ASIC, mk
      • Re: FPGA vs ASIC, Ray Andraka
      • Re: FPGA vs ASIC, Peter Alfke
      • Re: FPGA vs ASIC, Kim Enkovaara
• "SPI indirect" programming for any FPGA/CPLD, Antti
• Power supply filter capacitors, Nevo
  • Re: Power supply filter capacitors, Chris Maryan
    • Re: Power supply filter capacitors, Nevo
      • Re: Power supply filter capacitors, Gabor
      • Re: Power supply filter capacitors, MikeShepherd564
      • Re: Power supply filter capacitors, glen herrmannsfeldt
      • Re: Power supply filter capacitors, MikeShepherd564
      • Re: Power supply filter capacitors, Nevo
      • Message not available
      • Re: Power supply filter capacitors, MikeShepherd564
      • Message not available
      • Re: Power supply filter capacitors, Nevo
  • Re: Power supply filter capacitors, glen herrmannsfeldt
  • Re: Power supply filter capacitors, Nevo
    • Re: Power supply filter capacitors, John_H
      • Re: Power supply filter capacitors, Nevo
      • Re: Power supply filter capacitors, Frank Buss
      • Re: Power supply filter capacitors, Nevo
      • Re: Power supply filter capacitors, John_H
    • Re: Power supply filter capacitors, Symon
    • Re: Power supply filter capacitors, Brian Drummond
  • Re: Power supply filter capacitors, Frank Buss
    • Re: Power supply filter capacitors, Nevo
  • Re: Power supply filter capacitors, Rob
    • Re: Power supply filter capacitors, Nevo
      • Re: Power supply filter capacitors, Rob
      • Re: Power supply filter capacitors, glen herrmannsfeldt
  • Re: Power supply filter capacitors, Jim Granville
    • Re: Power supply filter capacitors, MikeShepherd564
      • Re: Power supply filter capacitors, Jim Granville
      • Re: Power supply filter capacitors, Nevo
      • Re: Power supply filter capacitors, Jim Granville
      • Re: Power supply filter capacitors, glen herrmannsfeldt
  • Re: Power supply filter capacitors, PeteS
• Question about the clocks power in XPower., Rebecca
• fgpa beginner, tirsys
  • Re: fgpa beginner, Mark McDougall
    • Re: fgpa beginner, svenand
      • Re: fgpa beginner, Vagant
      • Re: fgpa beginner, Eric Smith
• Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!, martin_pager
  • Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!, Antti
• ISE PACE Question, rg . jones
  • Re: ISE PACE Question, Gabor
• compile EDIF(generated by Celoxica DK4) using Quartus II, lyfieryflame
  • Re: compile EDIF(generated by Celoxica DK4) using Quartus II, Mike Treseler
  • Re: compile EDIF(generated by Celoxica DK4) using Quartus II, Subroto Datta
• Signetics N82F101F, tagough@xxxxxxxxx
  • Re: Signetics N82F101F, Jim Granville
    • Re: Signetics N82F101F, Andy
      • Re: Signetics N82F101F, Jim Granville
      • Re: Signetics N82F101F, tagough@xxxxxxxxx
      • Re: Signetics N82F101F, Jim Granville
• Re: Nios II, ThreadX, NetX, Nial Stewart
• is Quartus 7.1 really that S*** !?, Antti
  • Re: is Quartus 7.1 really that S*** !?, Antti
    • Re: is Quartus 7.1 really that S*** !?, Tommy Thorn
      • Re: is Quartus 7.1 really that S*** !?, Mark McDougall
      • Re: is Quartus 7.1 really that S*** !?, Antti
      • Re: is Quartus 7.1 really that S*** !?, fpgabuilder
      • Re: is Quartus 7.1 really that S*** !?, Antti
      • Re: is Quartus 7.1 really that S*** !?, fpgabuilder
      • Re: is Quartus 7.1 really that S*** !?, Antti
      • Re: is Quartus 7.1 really that S*** !?, Jim Granville
• xilinx spi flash programming, colin
  • Re: xilinx spi flash programming, Antti
  • Re: xilinx spi flash programming, Stef
    • Re: xilinx spi flash programming, Antti
      • Re: xilinx spi flash programming, Stef
      • Re: xilinx spi flash programming, colin
      • Re: xilinx spi flash programming, Antti
      • Re: xilinx spi flash programming, Stef
• builing a SPI interface in vhdl, techG
  • Re: builing a SPI interface in vhdl, Mark McDougall
  • Re: builing a SPI interface in vhdl, RCIngham
    • Re: builing a SPI interface in vhdl, Joseph Samson
  • Re: builing a SPI interface in vhdl, Ray Andraka
    • Re: builing a SPI interface in vhdl, Guru
  • Re: builing a SPI interface in vhdl, futzy . r
    • Re: builing a SPI interface in vhdl, techG
• MPMC2 NPI Help!, motty
  • Re: MPMC2 NPI Help!, MM
  • Re: MPMC2 NPI Help!, sovan
  • Re: MPMC2 NPI Help!, Guru
    • Re: MPMC2 NPI Help!, motty
      • Re: MPMC2 NPI Help!, sovan
      • Re: MPMC2 NPI Help!, motty
      • Re: MPMC2 NPI Help!, Guru
      • Re: MPMC2 NPI Help!, motty
      • Re: MPMC2 NPI Help!, MM
• Paper about selecting fixed point bit widths?, paragon . john
  • Re: Paper about selecting fixed point bit widths?, Duane Clark
  • Re: Paper about selecting fixed point bit widths?, Florian Stock
  • Re: Paper about selecting fixed point bit widths?, Marc Reinig
• MGT, shakith . fernando
  • Re: MGT, MM
    • Re: MGT, shakith . fernando
      • Re: MGT, MM
      • Re: MGT, MM
      • Re: MGT, shakith . fernando
• Multilinx and chipscope, michel . talon
• Programming Atmel dataflash with xilinx impact, Stef
  • Re: Programming Atmel dataflash with xilinx impact, Antti
    • Re: Programming Atmel dataflash with xilinx impact, Stef
• Addresses of subsystems, Vagant
  • Re: Addresses of subsystems, RCIngham
    • Re: Addresses of subsystems, Vagant
      • Re: Addresses of subsystems, MikeShepherd564
      • Re: Addresses of subsystems, Vagant
      • Re: Addresses of subsystems, Noway2
      • Re: Addresses of subsystems, Vagant
      • Re: Addresses of subsystems, John McCaskill
      • Re: Addresses of subsystems, Vagant
      • Re: Addresses of subsystems, John McCaskill
      • Re: Addresses of subsystems, John McCaskill
      • Re: Addresses of subsystems, Noway2
• Re: ERROR:NgdBuild:604 with user ipcore, ARRON
• Re: Changing refresh rate for DRAM while in operation?, MikeShepherd564
  • Re: Changing refresh rate for DRAM while in operation?, David Spencer
    • Re: Changing refresh rate for DRAM while in operation?, Peter Alfke
      • Re: Changing refresh rate for DRAM while in operation?, Antti
      • Re: Changing refresh rate for DRAM while in operation?, Jonathan Bromley
      • Re: Changing refresh rate for DRAM while in operation?, Peter Alfke
      • Re: Changing refresh rate for DRAM while in operation?, Jonathan Bromley
      • Re: Changing refresh rate for DRAM while in operation?, Jim Granville
      • Re: Changing refresh rate for DRAM while in operation?, Ray Andraka
      • Re: Changing refresh rate for DRAM while in operation?, glen herrmannsfeldt
      • Re: Changing refresh rate for DRAM while in operation?, Jonathan Bromley
      • Re: Changing refresh rate for DRAM while in operation?, glen herrmannsfeldt
      • Message not available
      • Re: Changing refresh rate for DRAM while in operation?, Andy
      • Re: Changing refresh rate for DRAM while in operation?, glen herrmannsfeldt
      • Re: Changing refresh rate for DRAM while in operation?, Andy
      • Re: Changing refresh rate for DRAM while in operation?, Hal Murray
      • Re: Changing refresh rate for DRAM while in operation?, Gabor
      • Re: Changing refresh rate for DRAM while in operation?, Ray Andraka
• XPS FIFO PLB device problems... (verilog), andrea . pellegrini
• Which demo board, Giki
• XILINX CDs, ola@xxxxxxx
• Re: Nios II, ThreadX, NetX Anyone?, Antti
• Alter RBF Compression, jtang
  • Re: Alter RBF Compression, MikeShepherd564
    • Re: Alter RBF Compression, jtang
      • Re: Alter RBF Compression, MikeShepherd564
      • Re: Alter RBF Compression, Sean Durkin
      • Re: Alter RBF Compression, jtang
      • Re: Alter RBF Compression, jtang
• ISE or EDK?, Vagant
  • Re: ISE or EDK?, Guru
  • Re: ISE or EDK?, Sean Durkin
  • Re: ISE or EDK?, MM
• microprocessor on fpga problems, Wei Wang
  • Re: microprocessor on fpga problems, Antti
    • Re: microprocessor on fpga problems, Jon Elson
      • Re: microprocessor on fpga problems, Antti
      • Re: microprocessor on fpga problems, Wei Wang
  • Re: microprocessor on fpga problems, ghelbig
    • Re: microprocessor on fpga problems, Andy
      • Re: microprocessor on fpga problems, ghelbig
• Building a Huffman codebook in VHDL, no_reply
  • Re: Building a Huffman codebook in VHDL, Antonio Pasini
    • Re: Building a Huffman codebook in VHDL, taco
      • Re: Building a Huffman codebook in VHDL, Antonio Pasini
• Protecting slices from GLOBAL_LOGIC0/GLOBAL_LOGIC1 usage?, Neil Steiner
  • Re: Protecting slices from GLOBAL_LOGIC0/GLOBAL_LOGIC1 usage?, Markus
    • Re: Protecting slices from GLOBAL_LOGIC0/GLOBAL_LOGIC1 usage?, Neil Steiner
      • Re: Protecting slices from GLOBAL_LOGIC0/GLOBAL_LOGIC1 usage?, Markus
• DVB-T/H help me ?, Kappa
• virtex-4 power consumption, sunry.zhang@xxxxxxxxx
  • Re: virtex-4 power consumption, austin
• xilinx 3adsp starter kit : where are demo and reference designs ?, rponsard@xxxxxxxxx
• Files produced by Quartus II compiler, scouselad
  • Re: Files produced by Quartus II compiler, Mike Treseler
  • Re: Files produced by Quartus II compiler, ghelbig
    • Re: Files produced by Quartus II compiler, scouselad
• LEDs, buttons and LCD, Vagant
  • Message not available
    • Re: LEDs, buttons and LCD, Vagant
  • Re: LEDs, buttons and LCD, spartan3wiz
    • Re: LEDs, buttons and LCD, Vagant
      • Re: LEDs, buttons and LCD, DialTone
      • Re: LEDs, buttons and LCD, Eric Crabill
      • Re: LEDs, buttons and LCD, Vagant
      • Re: LEDs, buttons and LCD, Vagant
• FPGA input level conversion, pbFJqKD
  • Re: FPGA input level conversion, Uwe Bonnes
    • Re: FPGA input level conversion, pbFJKD
      • Re: FPGA input level conversion, Uwe Bonnes
    • Re: FPGA input level conversion, Ben Jackson
  • Re: FPGA input level conversion, austin
    • Re: FPGA input level conversion, austin
      • Re: FPGA input level conversion, Uwe Bonnes
      • Re: FPGA input level conversion, austin
      • Re: FPGA input level conversion, Peter Alfke
• mess around with supply voltage to cyclone III, fpgazone
  • Re: mess around with supply voltage to cyclone III, David Spencer
  • Re: mess around with supply voltage to cyclone III, Jim Granville
• Wishbone Specification in Action, Gilbates
  • Re: Wishbone Specification in Action, Symon
  • Re: Wishbone Specification in Action, Patrick Dubois
• Fast Sampling of digital signals, aravind
  • Re: Fast Sampling of digital signals, Peter Alfke
  • Re: Fast Sampling of digital signals, cs_posting
    • Re: Fast Sampling of digital signals, aravind
      • Re: Fast Sampling of digital signals, Peter Alfke
  • Re: Fast Sampling of digital signals, pbFJKD
  • Re: Fast Sampling of digital signals, vasile
• FPGA pin swapping utility, cpandya
  • Re: FPGA pin swapping utility, Sean Durkin
    • Re: FPGA pin swapping utility, Andy
  • Re: FPGA pin swapping utility, ghelbig
    • Re: FPGA pin swapping utility, Jim Granville
  • Re: FPGA pin swapping utility, Andrew Burnside
• Re: VHDL trivia?, jan.kindt
  • Message not available
    • Re: VHDL trivia?, Symon
  • Message not available
    • Re: VHDL trivia?, Dave
      • Re: VHDL trivia?, evilkidder@xxxxxxxxxxxxxx
  • <Possible follow-ups>
  • Re: VHDL trivia?, Duane Clark
    • Re: VHDL trivia?, Jonathan Bromley
      • Message not available
      • Re: VHDL trivia?, Jonathan Bromley
      • Re: VHDL trivia?, evilkidder@xxxxxxxxxxxxxx
  • Re: VHDL trivia?, Jonathan Bromley
    • Message not available
      • Re: VHDL trivia?, Colin Paul Gloster
  • Re: VHDL trivia?, KJ
• Dynamic Reconfiguration books, GaLaKtIkUs™
  • Re: Dynamic Reconfiguration books, Antti
  • Re: Dynamic Reconfiguration books, Neil Steiner
    • Re: Dynamic Reconfiguration books, GaLaKtIkUs?
      • Re: Dynamic Reconfiguration books, Neil Steiner
      • Re: Dynamic Reconfiguration books, chnmyi
    • Re: Dynamic Reconfiguration books, mh
      • Re: Dynamic Reconfiguration books, GaLaKtIkUs?
• xilinx Edititons, xenix
  • Re: xilinx Edititons, Antti
  • Re: xilinx Edititons, Philip Potter
  • Re: xilinx Edititons, Alan Nishioka
    • Re: xilinx Edititons, John Williams
• What to consider for source synchronous clocking?, Ben
  • Re: What to consider for source synchronous clocking?, Gabor
  • Re: What to consider for source synchronous clocking?, David Spencer
    • Re: What to consider for source synchronous clocking?, Gabor
• systemc thread processes are called with the same thread in windows, CMOS
• Re: difference between XC5VLX50-1FFG676C and XC5VLX50-1FFG676CES, Mike Lewis
  • <Possible follow-ups>
  • Re: difference between XC5VLX50-1FFG676C and XC5VLX50-1FFG676CES, austin
    • Re: difference between XC5VLX50-1FFG676C and XC5VLX50-1FFG676CES, Eric Smith
      • Re: difference between XC5VLX50-1FFG676C and XC5VLX50-1FFG676CES, austin
• FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround, Antti
  • Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround, Dave
    • Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround, Antti
      • Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround, Mark McDougall
      • Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround, Marc Randolph
      • Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround, Antti
  • Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround, Mark McDougall
    • Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround, Antti
      • Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround, Kim Enkovaara
      • Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround, Antti
      • Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround, Thomas Stanka
      • Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround, Antti
  • Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround, neilla
    • Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround, Antti
      • Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround, Jim Granville
      • Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround, Antti
      • Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround, Antti
      • Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround, Jim Granville
      • Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround, Antti
      • Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround, Nial Stewart
      • Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround, Antti
      • Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround, Brian Davis
      • Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround, Antti
      • Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround, John McCaskill
      • Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround, Antti
• Reason for LUT1_L buffer insertion in Synplify EDIFs?, Neil Steiner
  • Re: Reason for LUT1_L buffer insertion in Synplify EDIFs?, John_H
    • Re: Reason for LUT1_L buffer insertion in Synplify EDIFs?, Neil Steiner
      • Re: Reason for LUT1_L buffer insertion in Synplify EDIFs?, Ray Andraka
      • Re: Reason for LUT1_L buffer insertion in Synplify EDIFs?, John_H
• xil_printf and %u specifier, Philip Potter
  • Re: xil_printf and %u specifier, Antti
    • Re: xil_printf and %u specifier, Philip Potter
• Xilinx Foundation 9.2 vhdl project won't run without executing cleanup project files, Dan K
• FPGA quiz 1&2, we have the answers and winners, Antti
  • Re: FPGA quiz 1&2, we have the answers and winners, Uwe Bonnes
    • Re: FPGA quiz 1&2, we have the answers and winners, Antti
  • Re: FPGA quiz 1&2, we have the answers and winners, Jim Granville
    • Re: FPGA quiz 1&2, we have the answers and winners, Antti
• High level FPGA work flow: available tool?, Maroc
  • Re: High level FPGA work flow: available tool?, csantos
    • Re: High level FPGA work flow: available tool?, Maroc
      • Re: High level FPGA work flow: available tool?, hans64
      • Re: High level FPGA work flow: available tool?, pivvosh
      • Re: High level FPGA work flow: available tool?, csantos
  • Re: High level FPGA work flow: available tool?, Allan Herriman
  • Re: High level FPGA work flow: available tool?, Mike Treseler
    • Re: High level FPGA work flow: available tool?, Andy
      • Re: High level FPGA work flow: available tool?, Mike Treseler
• IPs in MHS file, xenix
  • Re: IPs in MHS file, morphiend
    • Re: IPs in MHS file, xenix
• gold code - seed value, Manny
  • Re: gold code - seed value, Mike Treseler
• ethernet phy or mac, colin
  • Re: ethernet phy or mac, Mike Treseler
  • Re: ethernet phy or mac, Bryan
    • Re: ethernet phy or mac, colin
    • Re: ethernet phy or mac, Eric Smith
• FPGA to FPGA Bus, maxascent
  • Re: FPGA to FPGA Bus, Uncle Noah
  • Re: FPGA to FPGA Bus, RCIngham
    • Re: FPGA to FPGA Bus, Amontec, Larry
      • Re: FPGA to FPGA Bus, Eric Smith
      • Re: FPGA to FPGA Bus, Gabor
• Re: application about hardeware attributes, J.Wild
• RTM ERROR:fail to get the remote thread list., lzh08
• Xilinx:is it possible to install Impact 9.1only?, blisca
  • Re: Xilinx:is it possible to install Impact 9.1only?, cs_posting
    • R: Xilinx:is it possible to install Impact 9.1only?, blisca
      • Re: R: Xilinx:is it possible to install Impact 9.1only?, ghelbig
• FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2, Antti
  • Re: FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2, Laurent Pinchart
    • Re: FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2, Antti
      • Re: FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2, Laurent Pinchart
      • Re: FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2, avrbasic
      • Re: FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2, Laurent Pinchart
      • Re: FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2, Antti
      • Re: FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2, naughty . zeut
      • Re: FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2, avrbasic
      • Re: FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2, Laurent Pinchart
      • Re: FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2, avrbasic
      • Re: FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2, morphiend
      • Re: FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2, Antti
      • Re: FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2, morphiend
      • Re: FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2, mh
      • Re: FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2, mh
      • Re: FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2, Antti
• Xilinx FIFO Flag Question, motty
• Xilinx timing constraints incorrect?, paragon . john
  • Re: Xilinx timing constraints incorrect?, Mike Treseler
  • Re: Xilinx timing constraints incorrect?, Duane Clark
    • Re: Xilinx timing constraints incorrect?, paragon . john
      • Re: Xilinx timing constraints incorrect?, paragon . john
      • Re: Xilinx timing constraints incorrect?, Duane Clark
      • Re: Xilinx timing constraints incorrect?, paragon . john
      • Re: Xilinx timing constraints incorrect?, Mike Treseler
      • Re: Xilinx timing constraints incorrect?, Duane Clark
      • Re: Xilinx timing constraints incorrect?, paragon . john
      • Re: Xilinx timing constraints incorrect?, Mike Treseler
      • Re: Xilinx timing constraints incorrect?, paragon . john
      • Re: Xilinx timing constraints incorrect?, Duane Clark
• DWARF2 in MicroBlaze?, Steven Guccione
  • Re: DWARF2 in MicroBlaze?, Siva Velusamy
• FPGA quiz: what can be wrong, Antti
  • Re: FPGA quiz: what can be wrong, Jeff Cunningham
    • Re: FPGA quiz: what can be wrong, Antti
      • Re: FPGA quiz: what can be wrong, Jeff Cunningham
      • Re: FPGA quiz: what can be wrong, Antti
      • Re: FPGA quiz: what can be wrong, Jeff Cunningham
      • Re: FPGA quiz: what can be wrong, Antti
  • Re: FPGA quiz: what can be wrong, Amontec, Larry
    • Re: FPGA quiz: what can be wrong, Antti
      • Re: FPGA quiz: what can be wrong, Amontec, Larry
      • Re: FPGA quiz: what can be wrong, Antti
  • Re: FPGA quiz: what can be wrong, MM
    • Re: FPGA quiz: what can be wrong, Antti
      • Re: FPGA quiz: what can be wrong, JustJohn
      • Re: FPGA quiz: what can be wrong, Antti
      • Re: FPGA quiz: what can be wrong, MM
      • Re: FPGA quiz: what can be wrong, Antti
      • Re: FPGA quiz: what can be wrong, Matthew Hicks
      • Re: FPGA quiz: what can be wrong, Matthew Hicks
      • Re: FPGA quiz: what can be wrong, Antti
      • Re: FPGA quiz: what can be wrong, MM
      • Re: FPGA quiz: what can be wrong, avrbasic
      • Re: FPGA quiz: what can be wrong, glen herrmannsfeldt
      • Re: FPGA quiz: what can be wrong, Jim Granville
      • Re: FPGA quiz: what can be wrong, Antti
      • Re: FPGA quiz: what can be wrong, Jim Granville
      • Re: FPGA quiz: what can be wrong, Antti
      • Re: FPGA quiz: what can be wrong, Jim Granville
      • Re: FPGA quiz: what can be wrong, Evan Lavelle
      • Re: FPGA quiz: what can be wrong, avrbasic
      • Re: FPGA quiz: what can be wrong, avrbasic
      • Re: FPGA quiz: what can be wrong, Jim Granville
      • Re: FPGA quiz: what can be wrong, avrbasic
      • Re: FPGA quiz: what can be wrong, Manny
      • Re: FPGA quiz: what can be wrong, avrbasic
      • Re: FPGA quiz: what can be wrong, joerg
      • Re: FPGA quiz: what can be wrong, avrbasic
      • Re: FPGA quiz: what can be wrong, joerg
      • Re: FPGA quiz: what can be wrong, Antti
      • Re: FPGA quiz: what can be wrong, Jim Granville
      • Re: FPGA quiz: what can be wrong, Antti
      • Re: FPGA quiz: what can be wrong, Jim Granville
      • Re: FPGA quiz: what can be wrong, Antti
      • Re: FPGA quiz: what can be wrong, MM
      • Re: FPGA quiz: what can be wrong, Antti
      • Re: FPGA quiz: what can be wrong, backhus
      • Re: FPGA quiz: what can be wrong, Antti
      • Re: FPGA quiz: what can be wrong, Laurent Pinchart
      • Re: FPGA quiz: what can be wrong, Antti
      • Re: FPGA quiz: what can be wrong, Jim Granville
      • Re: FPGA quiz: what can be wrong, Douglas
      • Re: FPGA quiz: what can be wrong, Douglas
      • Re: FPGA quiz: what can be wrong, Antti
      • Re: FPGA quiz: what can be wrong, MM
      • Re: FPGA quiz: what can be wrong, Jim Granville
      • Re: FPGA quiz: what can be wrong, Evan Lavelle
  • Re: FPGA quiz: what can be wrong, Symon
    • Re: FPGA quiz: what can be wrong, Antti
      • Re: FPGA quiz: what can be wrong, Douglas
      • Re: FPGA quiz: what can be wrong, avrbasic
  • Re: FPGA quiz: what can be wrong, Ray Andraka
    • Re: FPGA quiz: what can be wrong, Antti
  • Re: FPGA quiz: what can be wrong, Matthieu
    • Re: FPGA quiz: what can be wrong, Antti
  • Re: FPGA quiz: what can be wrong, Phil Hays
    • Re: FPGA quiz: what can be wrong, Antti
  • Re: FPGA quiz: what can be wrong, Manny
  • Re: FPGA quiz: what can be wrong, Mike Treseler
    • Re: FPGA quiz: what can be wrong, Antti
  • Re: FPGA quiz: what can be wrong, backhus
    • Re: FPGA quiz: what can be wrong, Antti
    • Re: FPGA quiz: what can be wrong, Manny
      • Re: FPGA quiz: what can be wrong, Antti
      • Re: FPGA quiz: what can be wrong, Manny
      • Re: FPGA quiz: what can be wrong, avrbasic
  • Re: FPGA quiz: what can be wrong, Matthieu
    • Re: FPGA quiz: what can be wrong, Antti
      • Re: FPGA quiz: what can be wrong, Matthieu
      • Re: FPGA quiz: what can be wrong, avrbasic
      • Re: FPGA quiz: what can be wrong, Matthieu
      • Re: FPGA quiz: what can be wrong, Antti
  • Re: FPGA quiz: what can be wrong, Amontec, Larry
    • Re: FPGA quiz: what can be wrong, avrbasic
  • Re: FPGA quiz: what can be wrong, Amontec, Larry
    • Re: FPGA quiz: what can be wrong, avrbasic
      • Re: FPGA quiz: what can be wrong, cs_posting
      • Re: FPGA quiz: what can be wrong, Antti
  • Re: FPGA quiz: what can be wrong, Philip Potter
    • Re: FPGA quiz: what can be wrong, Antti
      • Re: FPGA quiz: what can be wrong, Brian Davis
      • Re: FPGA quiz: what can be wrong, Antti
      • Re: FPGA quiz: what can be wrong, Brian Davis
      • Re: FPGA quiz: what can be wrong, Antti
      • Re: FPGA quiz: what can be wrong, Brian Davis
      • Re: FPGA quiz: what can be wrong, Antti
      • Re: FPGA quiz: what can be wrong, Laurent Pinchart
      • Re: FPGA quiz: what can be wrong, Antti
      • Re: FPGA quiz: what can be wrong, Antti
      • Re: FPGA quiz: what can be wrong, Philip Potter
      • Re: FPGA quiz: what can be wrong, Antti
  • Re: FPGA quiz: what can be wrong, Bas Laarhoven
    • Re: FPGA quiz: what can be wrong, Antti
  • Re: FPGA quiz: what can be wrong, Amontec, Larry
    • Re: FPGA quiz: what can be wrong, Antti
    • Re: FPGA quiz: what can be wrong, Amontec, Larry
      • Re: FPGA quiz: what can be wrong, Antti
      • Re: FPGA quiz: what can be wrong, glen herrmannsfeldt
    • Re: FPGA quiz: what can be wrong, MikeShepherd564
      • Re: FPGA quiz: what can be wrong, Antti
  • Re: FPGA quiz: what can be wrong, Laurent Pinchart
    • Re: FPGA quiz: what can be wrong, Antti
      • Re: FPGA quiz: what can be wrong, Laurent Pinchart
      • Re: FPGA quiz: what can be wrong, avrbasic
      • Re: FPGA quiz: what can be wrong, Thomas Stanka
      • Re: FPGA quiz: what can be wrong, Antti
      • Re: FPGA quiz: what can be wrong, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
      • Re: FPGA quiz: what can be wrong, Antti
    • Re: FPGA quiz: what can be wrong, Antti
• Re: Clock boundary crossing, Mike Treseler
• profiling in modelsim, vishii4u
  • Re: profiling in modelsim, Mike Treseler
• FIFO depth, vishnuprasanth
  • Re: FIFO depth, backhus
    • Re: FIFO depth, Marlboro
      • Re: FIFO depth, backhus
  • Re: FIFO depth, Pranay
• Altera devices connecting to DDR memory., pgw
  • Re: Altera devices connecting to DDR memory., Sebastien Bourdeauducq
    • Re: Altera devices connecting to DDR memory., pgw
    • Re: Altera devices connecting to DDR memory., pgw
  • Re: Altera devices connecting to DDR memory., parekh . sh
    • Re: Altera devices connecting to DDR memory., pgw
• where to download latest systemc libararies?, e2point
  • Re: where to download latest systemc libararies?, HT-Lab
• MIG for Linux?, Duane Clark
  • Re: MIG for Linux?, pwie42
    • Re: MIG for Linux?, Duane Clark
      • Re: MIG for Linux?, Duane Clark
      • Re: MIG for Linux?, jacobusn@xxxxxxxxxx
      • Re: MIG for Linux?, Duane Clark
      • Re: MIG for Linux?, Duane Clark
      • Re: MIG for Linux?, Sandro
• Newbie,the simplest way to program an FPGA at home?, blisca
  • Re: Newbie,the simplest way to program an FPGA at home?, Sebastien Bourdeauducq
    • R: Newbie,the simplest way to program an FPGA at home?, blisca
      • Message not available
      • R: R: Newbie,the simplest way to program an FPGA at home?, blisca
      • Re: R: Newbie,the simplest way to program an FPGA at home?, backhus
  • Re: Newbie,the simplest way to program an FPGA at home?, Alan Nishioka
  • Re: Newbie,the simplest way to program an FPGA at home?, Andrew FPGA
    • R: Newbie,the simplest way to program an FPGA at home?, blisca
• Quartus II Web Edition License - SOPC Builder generation?, Eric
  • Re: Quartus II Web Edition License - SOPC Builder generation?, ghelbig
    • Re: Quartus II Web Edition License - SOPC Builder generation?, Eric
      • Re: Quartus II Web Edition License - SOPC Builder generation?, ghelbig
      • Re: Quartus II Web Edition License - SOPC Builder generation?, Eric
      • Re: Quartus II Web Edition License - SOPC Builder generation?, Mike Treseler
      • Re: Quartus II Web Edition License - SOPC Builder generation?, sendthis
      • Re: Quartus II Web Edition License - SOPC Builder generation?, sendthis
• Cyclone II on Altera DE2 Board - DRAM Timing on 18 inches?, Eric
  • Re: Cyclone II on Altera DE2 Board - DRAM Timing on 18 inches?, Mike Treseler
• NgdBuild:455 Multiple Drivers, lzkelley
  • Re: NgdBuild:455 Multiple Drivers, John_H
• Graphical VHDL Viewer ?, Stéphane Julhes
  • Re: Graphical VHDL Viewer ?, csantos
    • Re: Graphical VHDL Viewer ?, Stéphane Julhes
      • Re: Graphical VHDL Viewer ?, Mike Treseler
      • Re: Graphical VHDL Viewer ?, csantos
  • Re: Graphical VHDL Viewer ?, SKatsyuba
  • Re: Graphical VHDL Viewer ?, dadabuley@xxxxxxxxx
  • Re: Graphical VHDL Viewer ?, Nico Coesel
  • Re: Graphical VHDL Viewer ?, Alex
  • Re: Graphical VHDL Viewer ?, Patrick Dubois
• Xilinx OCM memory use limitations ?, SJU
  • Re: Xilinx OCM memory use limitations ?, xenix
  • Re: Xilinx OCM memory use limitations ?, morphiend
• Quartus II 7.2 web edition - Linux or not?, H. Peter Anvin
  • Re: Quartus II 7.2 web edition - Linux or not?, Mike Treseler
  • Re: Quartus II 7.2 web edition - Linux or not?, Kees Bakker
    • Re: Quartus II 7.2 web edition - Linux or not?, H. Peter Anvin
      • Re: Quartus II 7.2 web edition - Linux or not?, Sebastien Bourdeauducq
      • Re: Quartus II 7.2 web edition - Linux or not?, Mike Treseler
      • Re: Quartus II 7.2 web edition - Linux or not?, Tommy Thorn
      • Re: Quartus II 7.2 web edition - Linux or not?, cs_posting
      • Re: Quartus II 7.2 web edition - Linux or not?, Tommy Thorn
      • Re: Quartus II 7.2 web edition - Linux or not?, Kees Bakker
      • Re: Quartus II 7.2 web edition - Linux or not?, Uwe Bonnes
      • Re: Quartus II 7.2 web edition - Linux or not?, Eric Smith
      • Re: Quartus II 7.2 web edition - Linux or not?, NZG
• Xiinx ERROR:PhysDesignRules:10, Mark McDougall
  • Re: Xiinx ERROR:PhysDesignRules:10, beeraka@xxxxxxxxx
• FPGA tools under VMware or Parallels on a Mac?, Ron N.
  • Re: FPGA tools under VMware or Parallels on a Mac?, Jon Elson
    • Re: FPGA tools under VMware or Parallels on a Mac?, Ron N.
      • Re: FPGA tools under VMware or Parallels on a Mac?, beeraka@xxxxxxxxx
  • Re: FPGA tools under VMware or Parallels on a Mac?, svenand
  • Re: FPGA tools under VMware or Parallels on a Mac?, Tommy Thorn
• Cyclone II SSTL-2 on-chip resistors, Sebastien Bourdeauducq
  • Re: Cyclone II SSTL-2 on-chip resistors, austin
    • Re: Cyclone II SSTL-2 on-chip resistors, Sebastien Bourdeauducq
• HELP, how to time constraint part of a design?, DoVHDL
  • Re: HELP, how to time constraint part of a design?, John McCaskill
    • Re: HELP, how to time constraint part of a design?, DoVHDL
      • Re: HELP, how to time constraint part of a design?, DoVHDL
      • Re: HELP, how to time constraint part of a design?, Duane Clark
      • Re: HELP, how to time constraint part of a design?, DoVHDL
      • Re: HELP, how to time constraint part of a design?, Duane Clark
      • Re: HELP, how to time constraint part of a design?, fpgabuilder
      • Re: HELP, how to time constraint part of a design?, Duane Clark
      • Re: HELP, how to time constraint part of a design?, fpgabuilder
      • Re: HELP, how to time constraint part of a design?, llombard
      • Re: HELP, how to time constraint part of a design?, Brian Drummond
      • Re: HELP, how to time constraint part of a design?, llombard
• What happened to Confluence and HDCaml?, rubyfan
  • Re: What happened to Confluence and HDCaml?, Philipp Klaus Krause
    • Re: What happened to Confluence and HDCaml?, Phil Tomson
      • Re: What happened to Confluence and HDCaml?, Philipp Klaus Krause
      • Re: What happened to Confluence and HDCaml?, Philipp Klaus Krause
• Compiler Options, xenix
  • Re: Compiler Options, ghelbig
  • Re: Compiler Options, Jon Beniston
• Unrouted nets (Xilinx FPGA Editor), Ju, Jian
  • Re: Unrouted nets (Xilinx FPGA Editor), dadabuley@xxxxxxxxx
    • Re: Unrouted nets (Xilinx FPGA Editor), Marlboro
• UK Supplier XILINX spartan 3 development board??, dan . walmsley
  • Re: UK Supplier XILINX spartan 3 development board??, John Adair
  • Re: UK Supplier XILINX spartan 3 development board??, John Adair
  • Re: UK Supplier XILINX spartan 3 development board??, Symon
    • Re: UK Supplier XILINX spartan 3 development board??, Mike Harrison
      • Re: UK Supplier XILINX spartan 3 development board??, Symon
      • Re: UK Supplier XILINX spartan 3 development board??, Mike Harrison
• Xcell Article on 1.2Gsamples/sec FFT, Andrew FPGA
  • Re: Xcell Article on 1.2Gsamples/sec FFT, Guenter Dannoritzer
    • Re: Xcell Article on 1.2Gsamples/sec FFT, Ray Andraka
  • Re: Xcell Article on 1.2Gsamples/sec FFT, Ray Andraka
• Timing Constraint Question, motty
  • Re: Timing Constraint Question, morphiend
• Re: Low-level FPGA programming?, Adam Megacz
• Re: Open-Source VHDL Synthesis for FPSLIC?, Adam Megacz
  • <Possible follow-ups>
  • Re: Open-Source VHDL Synthesis for FPSLIC?, Adam Megacz
  • Re: Open-Source VHDL Synthesis for FPSLIC?, Adam Megacz
• Legacy support of a Max 7000S, Noway2
  • Re: Legacy support of a Max 7000S, Jim Granville
    • Re: Legacy support of a Max 7000S, Noway2
• DDR DIMM clock distribution, pgw
  • Re: DDR DIMM clock distribution, Brian Drummond
• 8B/10B Xilinx Paper, ALuPin@xxxxxx
  • Re: 8B/10B Xilinx Paper, mk
    • Re: 8B/10B Xilinx Paper, ALuPin@xxxxxx
      • Re: 8B/10B Xilinx Paper, ALuPin@xxxxxx
• code coverage in modesim se 6.1f, kalvarajesh2003
• Starting FPGA, dan . walmsley
  • Re: Starting FPGA, austin
  • Re: Starting FPGA, Brian Drummond
    • Re: Starting FPGA, svenand
  • Re: Starting FPGA, pdudley1@xxxxxxxxxxx
• CY22393, axalay
  • Re: CY22393, Gabor
• Need suggestion on FPGA kit, yeah
  • Re: Need suggestion on FPGA kit, John_H
  • Re: Need suggestion on FPGA kit, austin
    • Re: Need suggestion on FPGA kit, Antti
      • Re: Need suggestion on FPGA kit, austin
      • Re: Need suggestion on FPGA kit, yeah
      • Re: Need suggestion on FPGA kit, John Adair
      • Re: Need suggestion on FPGA kit, Austin Lesea
• Neural Coprocessor with Xilinx EDK, Moikel
• Cyclone II - PLL differential output, pgw
  • Re: Cyclone II - PLL differential output, Górski Adam
    • Re: Cyclone II - PLL differential output, pgw
• kicad or orcad virtex5 symbol, michel . talon
  • Re: kicad or orcad virtex5 symbol, ghelbig
    • Re: kicad or orcad virtex5 symbol, michel . talon
  • Re: kicad or orcad virtex5 symbol, schsym
  • Re: kicad or orcad virtex5 symbol, colin
• code coverage in modelsim_se, kalvarajesh2003
• Re: [ANN] FPGAOptim - Do you know where your slices are going...?, Martin Thompson
  • Re: [ANN] FPGAOptim - Do you know where your slices are going...?, Laurent Pinchart
    • Re: [ANN] FPGAOptim - Do you know where your slices are going...?, Martin Thompson
      • Re: [ANN] FPGAOptim - Do you know where your slices are going...?, Laurent Pinchart
• JTAG interconnect testing, prototypes, Tony Burch
  • Re: JTAG interconnect testing, prototypes, ghelbig
  • Re: JTAG interconnect testing, prototypes, BobW
  • Re: JTAG interconnect testing, prototypes, Amontec, Larry
    • Re: JTAG interconnect testing, prototypes, beeraka@xxxxxxxxx
      • Re: JTAG interconnect testing, prototypes, skswrus
    • Re: JTAG interconnect testing, prototypes, skswrus
  • Re: JTAG interconnect testing, prototypes, John McCaskill
  • Re: JTAG interconnect testing, prototypes, Uwe Bonnes
  • Re: JTAG interconnect testing, prototypes, Tony Burch
• FiberChannel SOF, Walters
  • Re: FiberChannel SOF, Nony Moose
  • Re: FiberChannel SOF, Ken Ryan
• Opteron performance tuning (for Quartus / Linux)?, jjohnson
  • Re: Opteron performance tuning (for Quartus / Linux)?, H. Peter Anvin
  • Re: Opteron performance tuning (for Quartus / Linux)?, ghelbig
  • Re: Opteron performance tuning (for Quartus / Linux)?, Thomas Womack
    • Re: Opteron performance tuning (for Quartus / Linux)?, jjohnson
  • Re: Opteron performance tuning (for Quartus / Linux)?, Systemv User
• Virtex 13?, BobW
  • Re: Virtex 13?, Jim Granville
    • Re: Virtex 13?, Marc Randolph
  • Re: Virtex 13?, austin
    • Re: Virtex 13?, Ken Ryan
• Re: Altera PowerPlay Early Power Estimator Spreadsheet and MXCOMCT2.OCX, vaughnbetz
• Re: Using PlanAhead for Partial Reconfiguration, hiroyuki.kawai@xxxxxxxxx
• Re: XUPV2P from digilentinc, spartan3wiz
  • Re: XUPV2P from digilentinc, John_H
    • Re: XUPV2P from digilentinc, emeb
      • Re: XUPV2P from digilentinc, johnzulu [at] yahoo . com
  • Re: XUPV2P from digilentinc, johnzulu [at] yahoo . com
  • <Possible follow-ups>
  • Re: XUPV2P from digilentinc, cs_posting
• How to do one hot state machine in verilog for Xilinx V5 using XST, cpandya
  • Re: How to do one hot state machine in verilog for Xilinx V5 using XST, John_H
    • Re: How to do one hot state machine in verilog for Xilinx V5 using XST, cpandya
      • Re: How to do one hot state machine in verilog for Xilinx V5 using XST, Jarek Rozanski
      • Re: How to do one hot state machine in verilog for Xilinx V5 using XST, Jeff Cunningham
      • Re: How to do one hot state machine in verilog for Xilinx V5 using XST, Gabor
• Daisy chaining FPGA with CPLDs, pomerado@xxxxxxxxxxx
  • Re: Daisy chaining FPGA with CPLDs, John_H
  • Re: Daisy chaining FPGA with CPLDs, Andrew Holme
    • Re: Daisy chaining FPGA with CPLDs, KJ
  • Re: Daisy chaining FPGA with CPLDs, Peter Wallace
• Problem about ADV7181B debugging, commone
• Best way to export XPS project to ISE?, cpope
  • Re: Best way to export XPS project to ISE?, morphiend
• xup-v2p: Only USB 1.1, joerg
  • Re: xup-v2p: Only USB 1.1, John_H
• JPEG-LS hardware implementation, cms
  • Re: JPEG-LS hardware implementation, zeeman_be
    • Re: JPEG-LS hardware implementation, cms
      • Re: JPEG-LS hardware implementation, Pete Fraser
      • Re: JPEG-LS hardware implementation, Simon
      • Re: JPEG-LS hardware implementation, Weng Tianxiang
      • Re: JPEG-LS hardware implementation, cms
      • Re: JPEG-LS hardware implementation, Weng Tianxiang
      • Re: JPEG-LS hardware implementation, cms
• Optimized bitcounting on FPGA, Steven Derrien
  • Re: Optimized bitcounting on FPGA, Ray Andraka
    • Re: Optimized bitcounting on FPGA, Peter Alfke
    • Re: Optimized bitcounting on FPGA, Steven Derrien
      • Re: Optimized bitcounting on FPGA, glen herrmannsfeldt
  • Re: Optimized bitcounting on FPGA, Andreas Schwarz
    • Re: Optimized bitcounting on FPGA, comp.arch.fpga
    • Re: Optimized bitcounting on FPGA, Peter Alfke
• Companies that Manufacture Multi-FPGA Hardware, O. Olson
  • Re: Companies that Manufacture Multi-FPGA Hardware, maxascent
  • Re: Companies that Manufacture Multi-FPGA Hardware, John Aderseen
  • Re: Companies that Manufacture Multi-FPGA Hardware, comp.arch.fpga
  • Re: Companies that Manufacture Multi-FPGA Hardware, cms
  • Re: Companies that Manufacture Multi-FPGA Hardware, Matthew Hicks
  • Re: Companies that Manufacture Multi-FPGA Hardware, John Adair
    • Re: Companies that Manufacture Multi-FPGA Hardware, O. Olson
• XUPV2P serial connection through serial-to-usb cable, Rhishi
  • Re: XUPV2P serial connection through serial-to-usb cable, ghelbig
• Detecting if an error happened in ModelSim, Chris Maryan
  • Re: Detecting if an error happened in ModelSim, KJ
    • Re: Detecting if an error happened in ModelSim, Chris Maryan
  • Re: Detecting if an error happened in ModelSim, Mike Treseler
    • Re: Detecting if an error happened in ModelSim, Chris Maryan
      • Re: Detecting if an error happened in ModelSim, Mike Treseler
      • Re: Detecting if an error happened in ModelSim, Chris Maryan
      • Re: Detecting if an error happened in ModelSim, Mike Treseler
      • Re: Detecting if an error happened in ModelSim, Chris Maryan
• Tcl - Xilinx - ISE - WindowsXP, jerzy.gbur@xxxxxxxxx
  • Re: Tcl - Xilinx - ISE - WindowsXP, Arnim
    • Re: Tcl - Xilinx - ISE - WindowsXP, jerzy.gbur@xxxxxxxxx
      • Re: Tcl - Xilinx - ISE - WindowsXP, jerzy.gbur@xxxxxxxxx
      • Re: Tcl - Xilinx - ISE - WindowsXP, Evan Lavelle
• Partial/Incorrect configuration of FPGA from flash PROM., christovt
  • Re: Partial/Incorrect configuration of FPGA from flash PROM., Gabor
• Re: Bug in Synplify?, Thomas Stanka
  • <Possible follow-ups>
  • Re: Bug in Synplify?, Thomas Stanka
    • Re: Bug in Synplify?, Andy
• Re: load/read/ commands assembly PowerPC. Help Needed!, xenix
• Any better ways for interfacing fpga with dynamic memory?, Wei Wang
• CFP: SCALABLE COMPUTING. Special Issue on High Performance Reconfigurable Computing (HPRC), eferrer
  • Re: CFP: SCALABLE COMPUTING. Special Issue on High Performance Reconfigurable Computing (HPRC), eferrer
  • Re: CFP: SCALABLE COMPUTING. Special Issue on High Performance Reconfigurable Computing (HPRC), eferrer
• Re: Programming the ARM7 used to download our Xilinx FPGA, Amontec, Larry
• Virtex4: ISERDES -> FIFO -> BlockRAM fails, jobeck
• ALTERA Quartus 7.2 under MS Vista, Pszemol
  • Re: ALTERA Quartus 7.2 under MS Vista, Rob
• Re: memory in spartan 3 fpga, pete
• Re: Planning to switch to FPGA domain, any advice would be highly appreciated, Narsi
• Test and Measurements - Large FPGA, Narsi
  • Re: Test and Measurements - Large FPGA, Symon
  • Re: Test and Measurements - Large FPGA, comp.arch.fpga
  • Re: Test and Measurements - Large FPGA, Narsi
    • Re: Test and Measurements - Large FPGA, Mike Treseler
  • Re: Test and Measurements - Large FPGA, Jim Granville
    • Re: Test and Measurements - Large FPGA, Gabor
• Spartan3E DDR clock feedback, Guru
• Re: www.fpga-games.com website died?, Eric Crabill
  • Re: www.fpga-games.com website died?, Symon
• Re: FPGA NTSC signal with 2 resistors and PWM, Jon Elson
  • Re: FPGA NTSC signal with 2 resistors and PWM, glen herrmannsfeldt
    • Re: FPGA NTSC signal with 2 resistors and PWM, Jecel
  • <Possible follow-ups>
  • Re: FPGA NTSC signal with 2 resistors and PWM, Jecel
    • Re: FPGA NTSC signal with 2 resistors and PWM, Mike Treseler
      • Re: FPGA NTSC signal with 2 resistors and PWM, Jecel
  • Re: FPGA NTSC signal with 2 resistors and PWM, Nial Stewart
    • Re: FPGA NTSC signal with 2 resistors and PWM, Antti
    • Re: FPGA NTSC signal with 2 resistors and PWM, glen herrmannsfeldt
• Re: 2 leg crystal on FPGA: Lattice vs Xilinx, Jon Elson
  • Re: 2 leg crystal on FPGA: Lattice vs Xilinx, Antti
  • <Possible follow-ups>
  • Re: 2 leg crystal on FPGA: Lattice vs Xilinx, Jon Elson
  • Re: 2 leg crystal on FPGA: Lattice vs Xilinx, Jim Granville
  • Re: 2 leg crystal on FPGA: Lattice vs Xilinx, Jim Granville
  • Re: 2 leg crystal on FPGA: Lattice vs Xilinx, lb . edc
  • Re: 2 leg crystal on FPGA: Lattice vs Xilinx, Jim Granville
• Count Leading Zero (CLZ) possible by MicroBlaze??, armandolou
  • Re: Count Leading Zero (CLZ) possible by MicroBlaze??, glen herrmannsfeldt
    • Re: Count Leading Zero (CLZ) possible by MicroBlaze??, Gabor
      • Re: Count Leading Zero (CLZ) possible by MicroBlaze??, armandolou
      • Message not available
      • Re: Count Leading Zero (CLZ) possible by MicroBlaze??, Anacrom
      • Re: Count Leading Zero (CLZ) possible by MicroBlaze??, Göran Bilski
• Error in simple code, plz help, VladimirM
  • Re: Error in simple code, plz help, beeraka@xxxxxxxxx
  • Re: Error in simple code, plz help, backhus
• Re: PowerPC Simulation, motty
• Re: Own soft-processor, Tommy Thorn
  • Re: Own soft-processor, Andrew Burnside
  • <Possible follow-ups>
  • Re: Own soft-processor, Hal Murray
  • Re: Own soft-processor, cs_posting
• Synplicity and the Xilinx MAP Memory Monster, Tim (one of many)
  • Re: Synplicity and the Xilinx MAP Memory Monster, Brian Drummond
  • Re: Synplicity and the Xilinx MAP Memory Monster, John_H

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newsgroups.derkeiler.com  > Archive  > Comp  > comp.arch.fpga  > 2007-10