Re: 2 leg crystal on FPGA: Lattice vs Xilinx

On 30 Sep., 03:24, Ray Andraka <r...@xxxxxxxxxxx> wrote:
johnp wrote:

I'd be happy if Xilinx would simply provide a free running, loosely
spec'd clock in the FPGAs
that a designer could use for non-critical design. They could spec it
as "it runs at some
frequency between 5 and 30 MHz and will drift with temperature/
voltage, you can't set it,
you can only use it." If they would let you use the Master Mode
programming clock inside
the design, I'd be happy. I don't care about the frequency, I just
want a free running clock.

No crystal pads, no clock divider, just a ring oscillator within a
reasonable frequency range.

John Providenza

Virtex4 actually has this. It isn't well documented, but it is there.
Xilinx uses it for the NBTI fix in V4 devices. It does have an internal
purpose, I think it was for one of the configuration download modes.

I don't recall off-hand the magic incantation to use it, I'd have to
find it in my design files. I think you have to make a hard macro in
FPGA editor to get at it.- Zitierten Text ausblenden -

- Zitierten Text anzeigen -

yes PMV primitive can be used as free running clock, but its tricky to
use it as it xilinx undocumented feature

Antti

.

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