Re: 2 leg crystal on FPGA: Lattice vs Xilinx

Peter Alfke <alfke@xxxxxxxxxxxxx> wrote:

On Sep 28, 5:05 pm, John Adair <g...@xxxxxxxxxxxxxxxx> wrote:
Austin

Might be worth making the suggestion to your sister grouping of GPD of
adding a dedicated oscillator crcuit to their range of products. Given
a lot of micros do that already there would be some logic in adding
such a circuit in the future to the low cost sector FPGA families.

John, "been there, done that".
XC3000 used to have a single-stage dedicated inverter, exactly for
that purpose. It caused us a lot of support grief. Between 32 kHz and
100 MHz, there is a big variation in xtals, and there also was a
sensitivity to Vcc ramp-up rate. Nobody wants a circuit to work "most
of the time".
I also remember that many of the Intel mask revisions of the 8051 were
oscillator-related. (We second-sourced that at AMD)
My advice has always been: spend a few pennies on an oscillator
circuit made by specialists for a special purpose. And definitely do

Xilinx could buy such a circuit as IP and integrate it. The parts
containing non-volatile configuration memory would benefit greatly and
could potentially replace microcontrollers. A PLL would even be better
and also reduces the range of crystal frequencies that need to be
supported. 4MHz to 16MHz would be enough.

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