Re: 2 leg crystal on FPGA: Lattice vs Xilinx

On 29 Sep., 04:49, Peter Alfke <al...@xxxxxxxxxxxxx> wrote:
On Sep 28, 5:05 pm, John Adair <g...@xxxxxxxxxxxxxxxx> wrote:> Austin

Might be worth making the suggestion to your sister grouping of GPD of
adding a dedicated oscillator crcuit to their range of products. Given
a lot of micros do that already there would be some logic in adding
such a circuit in the future to the low cost sector FPGA families.

John, "been there, done that".
XC3000 used to have a single-stage dedicated inverter, exactly for
that purpose. It caused us a lot of support grief. Between 32 kHz and
100 MHz, there is a big variation in xtals, and there also was a
sensitivity to Vcc ramp-up rate. Nobody wants a circuit to work "most
of the time".
I also remember that many of the Intel mask revisions of the 8051 were
oscillator-related. (We second-sourced that at AMD)
My advice has always been: spend a few pennies on an oscillator
circuit made by specialists for a special purpose. And definitely do
not abuse a multi-stage I/O circuit to be the xtal inverter circuit.
Far too much gain and uncontrolled phase changes at very high
frequencies.
Peter Alfke

a few pennies?
FPGA prices start from 2 USD, so extra 20 penny for the oscillator is
over 10% of the FPGA cost.

there is magic thing called specification: if the oscillator would
work reliable with 10 to 100MHz range then its sufficient to include
that in the spec, and no-one would expect it to work with 32khz

adding 32khz support would require 1 extra config bit to select LP vs
HS oscillator, very similar to fuse options by Atmel flash MCUs.

sure its additional engineering but.. MANY MANY MCU companies are
including this option, and it is working and doable. I cant imaging it
would not have been possible to test it without extra mask cost to
xilinx, by addint 2 test pins during say V-4 initial testing. how many
mask revisions was made? if the osc circuit would have been included
xilinx would have plenty of time (mask revisions) to fine tune it. and
in the case of failure those 2 magic pins would have "reserved" or GND
marking in final data***.

simple. just a matter of decision.

Antti









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