Re: Bug in Synplify?

Hi,

On 27 Sep., 21:20, Andy <jonesa...@xxxxxxxxxxx> wrote:
Can you post some code? It is difficult to understand what you want,
let alone the problem with what you are getting, without seeing some
example code. Also, does your target even support async reset on RAMs?

Just to clearify:
I have a code which Synplify detects as Ram in compile step.
If Synplify didn't use a RAM later to implement this structure but a
set of pure registers (either due to resource usage, time contraints
or because I use the pragma" syn_ramstyle register" in VHDL-code) I
get some functional correct result but the solution uses way too much
registers.

Below is a sample code in VHDL which will result to ram infering in
the first place(not checked for correctness of syntax)
The example below should fit in 3 bit counter and 6x8 FF with asynch
reset. I got a result which uses nearly twice the number of FF
(without asynch. reset) in order to provide the same functionality
with a slightly more complex code, but no need to have that much
register doubling for load balance or anything like that. A lot of
registers are used in order to manage the "asynch reset" in a synchron
way.

TYPE array_type is ARRAY (1 to 6) of std_ulogic_vector(7 downto 0);
signal my_array : array_type;
attribute syn_ramstyle of my_array is register;
....
process (clk, rst)
variable cnt: integer range 0 to 7;
if rst='0' then
my_array <= (others => (others =>'0'));
cnt :=0;
elsif rising_edge(clk) then
if load = '1' then
my_array(cnt) <= an_input;
end if;
.....

.

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