Re: Bug in Synplify?
- From: Thomas Stanka <usenet_10@xxxxxxxxxxxxx>
- Date: Thu, 27 Sep 2007 22:46:15 -0700
On 27 Sep., 21:20, Andy <jonesa...@xxxxxxxxxxx> wrote:
On Sep 27, 12:45 am, Thomas Stanka <usenet...@xxxxxxxxxxxxx> wrote:
Hi,
I have a behavior in Synplify Pro for Actel Fpgas I would call a bug
(seen in each old version I could find up to the newest 9.0)
If having a register file which is accessed only in words with fixed
width and an asynchronous reset, synplify detects a ram structure in
the compile step. If the ram isn't used later (due to constrained ram-
style register, or due to resource usage), synplify uses FF without an
asynchronous reset for the register bank and a hell of logic to force
the circuit to behave like it uses asynchnous reset. I have a simple
example(6x8 bit), were synplicity uses twice the register normaly
necessary. This behavior is only seen when using a technology which
provides ram at all. So I like to know if there is a reason to
consider this a problem of the tech library? Is there anybody out
seeing the same behavior in other technologies than Actel (APA, AX)?
regards Thomas
Can you post some code? It is difficult to understand what you want,
let alone the problem with what you are getting, without seeing some
example code. Also, does your target even support async reset on RAMs?
Just to clearify:
I have a code which Synplify detects as Ram in compile step.
If Synplify didn't use a RAM later to implement this structure but a
set of pure registers (either due to resource usage, time contraints
or because I use the pragma" syn_ramstyle register" in VHDL-code.
A example code in VHDL
TYPE array_type is ARRAY (1 to 6) of std_ulogic_vector(7 downto 0);
signal my_array : array_type;
....
process (clk, rst)
if rst='0' then
my_array <= (others => (others =>'0'));
elsif rising_edge(clk) then
.
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