Re: Bug in Synplify?

Thomas Stanka wrote:
Hi,

I have a behavior in Synplify Pro for Actel Fpgas I would call a bug
(seen in each old version I could find up to the newest 9.0)

If having a register file which is accessed only in words with fixed
width and an asynchronous reset, synplify detects a ram structure in
the compile step. If the ram isn't used later (due to constrained ram-
style register, or due to resource usage), synplify uses FF without an
asynchronous reset for the register bank and a hell of logic to force
the circuit to behave like it uses asynchnous reset. I have a simple
example(6x8 bit), were synplicity uses twice the register normaly
necessary. This behavior is only seen when using a technology which
provides ram at all. So I like to know if there is a reason to
consider this a problem of the tech library? Is there anybody out
seeing the same behavior in other technologies than Actel (APA, AX)?

regards Thomas

If you don't want a RAM attempted in the first place but the tool is trying anyway, use the syn_ramstyle attribute to force flops, allowing a clean async reset, perhaps.
.

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