Re: Physical Design Contribution to FPGA/CPLD success

acd wrote:

CPLDs and FPGAs both make (or made) use of "non-standard"
implementation
of digital circuits, namely wired-OR and pass-transistors.
Both techniques are much more difficult to use in standard cell ASICs
or gate arrays.
Therefore, one could argue that the use of these methods reduced the
area and speed
overhead induced by the programmability.
So while many ASICs that have been replaced by FPGAs would not have
used the methods,
the CPLDs/FPGAs did.

How strong do you think was and is this effect?
Would FPGAs have been successfull, if they had been implemented with
vanilla CMOS gates and latches?
Or better, how much smaller the success story of FPGAs would have
been without the use of pass transistors in LUTs and routing?

It's not clear what you mean by 'vanilla CMOS gates and latches' ?

CPLDs were quite different from FPGAs in structure, and Philips
were the leaders in 'true CMOS' CPLDs, which now sees Atmel/Lattice/Xilinx(via Philips) offering CMOS CPLDs.

FPGAs have always needed MUX elements (your pass-transistor)
as they have always had a routing element.

If you again look back at CPLDs, you will see above a certain size,
they also have recently moved to MUX/Tiled designs - so that gives
you the answer. Below a certain size, 'vanilla CMOS' makes sense,
and above that level, you need MUX's to stay efficent.

A factor in that branch, will also be the Software experience
that exists in FPGA design tools. Whilst there may possibly
have been another middle structure, the mature design flows in
the FPGA camp, made that jump natural for CPLDs.

-jg

.

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