Re: VHDL Synthesis Error
ray.delvecchio@xxxxxxxxx wrote:
I am new to VHDL, so I'm not quite sure why I'm getting this error or
how I should go about fixing it.
Maybe load_prev <= load; should be inside the clocked IF.
In general, to fix problems like this requires a vhdl simulator.
You would get more responses by posting to comp.lang.vhdl
-- Mike Treseler
.
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