VHDL Synthesis Error
- From: ray.delvecchio@xxxxxxxxx
- Date: Mon, 10 Sep 2007 16:00:26 -0000
Hello all,
I am trying to implement a network adapter that sends small packets to
and from FPGA boards using VHDL. I want to download this and test it
out, but I am getting the following synthesis error when I try to
generate the bit file in Xilinx:
Related source file is "usa/delvecch/project1/Packet_Gen.vhd"
ERROR:Xst:2108 - Logic for signal <packet_out> is controlled by a
clock but does not appear to be a valid sequential description
ERROR:Xst:1431 - Failed to synthesize unit <Packet_Gen>.
Here is my code for the packet generation module:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity Packet_Gen is
port( clkin: in std_logic;
reset: in std_logic;
load: in std_logic;
fwd: in std_logic;
dest_addr: in std_logic_vector (1 downto 0);
packet_fwd: in std_logic_vector (5 downto 0);
packet_out: out std_logic_vector (5 downto 0));
end Packet_Gen;
architecture behavioral of Packet_Gen is
signal load_prev: std_logic := '0';
begin
PG_proc: process (clkin, reset) is
begin
if (reset = '0') then
packet_out <= "000001";
elsif (clkin'event and clkin = '1') then
if (fwd = '0') then
if (load_prev = '0' and load = '1')
then
packet_out <= "100" &
dest_addr & '1';
else
packet_out <= "000001";
end if;
else
packet_out <= packet_fwd;
end if;
end if;
load_prev <= load;
end process PG_proc;
end behavioral;
To briefly describe the operation, if reset is 0 (active low), load
packet_out with an inactive packet ("000001"). For this design, a
packet is transmitted every rising edge of the clock cycle. If fwd is
0, then a packet is not being forwarded from another adapter, and a
new packet must be created. If a rising edge is detected on the load
signal, an active packet is created, otherwise an inactive packet is
created. If fwd is 1, simply forward the input packet (packet_fwd) to
the output (packet_out).
I am new to VHDL, so I'm not quite sure why I'm getting this error or
how I should go about fixing it. Any suggestions? I appreciate any
help that you may have for me. Thanks.
.
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