comp.arch.fpga

• Thread Index

---

• Re: FPGA Archives
  • From: Philip Freidin
• Planning to switch to FPGA domain, any advice would be highly appreciated
  • From: To: Kshitij Arora <
• Re: job inquiry; entry/trainee FPGA/ASIC designer
  • From: Symon
• Re: PowerPC Simulation
  • From: Ken Ryan
• Re: Walking 1's
  • From: PeteS
• Re: XUPV2P from digilentinc
  • From: vasile
• Re: Walking 1's
  • From: MikeShepherd564
• Re: XUPV2P from digilentinc
  • From: johnzulu [at] yahoo . com
• Re: Walking 1's
  • From: Jonathan Bromley
• Re: XUPV2P from digilentinc
  • From: Brian Drummond
• Walking 1's
  • From: Walters
• Re: Own soft-processor
  • From: Andrew Burnside
• Re: Own soft-processor
  • From: Tommy Thorn
• Re: Own soft-processor
  • From: sdf
• www.fpga-games.com website died?
  • From: Antti
• Re: 2 leg crystal on FPGA: Lattice vs Xilinx
  • From: Antti
• Re: 2 leg crystal on FPGA: Lattice vs Xilinx
  • From: Ray Andraka
• Re: 2 leg crystal on FPGA: Lattice vs Xilinx
  • From: Ray Andraka
• Re: FPGA NTSC signal with 2 resistors and PWM
  • From: Jecel
• Re: XST corrupts my state machine. Only disabling FSM encoding helps
  • From: Helpme
• Re: 2 leg crystal on FPGA: Lattice vs Xilinx
  • From: Nico Coesel
• Re: 2 leg crystal on FPGA: Lattice vs Xilinx
  • From: Antti
• Re: 2 leg crystal on FPGA: Lattice vs Xilinx
  • From: KJ
• Re: 2 leg crystal on FPGA: Lattice vs Xilinx
  • From: Phil Hays
• Re: 2 leg crystal on FPGA: Lattice vs Xilinx
  • From: John_H
• Re: XUPV2P from digilentinc
  • From: John_H
• Re: Own soft-processor
  • From: emu
• Re: job inquiry; entry/trainee FPGA/ASIC designer
  • From: John McCaskill
• Re: XUPV2P from digilentinc
  • From: emu
• Re: 2 leg crystal on FPGA: Lattice vs Xilinx
  • From: John Adair
• Re: 2 leg crystal on FPGA: Lattice vs Xilinx
  • From: johnp
• Re: job inquiry; entry/trainee FPGA/ASIC designer
  • From: theanonymous83
• Re: XUPV2P from digilentinc
  • From: johnzulu [at] yahoo . com
• Re: [offtopic] job inquiry; entry/trainee FPGA/ASIC designer
  • From: Symon
• Re: please help me for vhdl code of temprature controller
  • From: Nicolas Matringe
• Re: Own soft-processor
  • From: Nicolas Matringe
• please help me for vhdl code of temprature controller
  • From: nanaware_amit
• Re: Never buy Altera!!!!
  • From: Gabor
• Re: XUPV2P from digilentinc
  • From: stephen.craven@xxxxxxxxx
• Re: Own soft-processor
  • From: Jarek Rozanski
• Re: 2 leg crystal on FPGA: Lattice vs Xilinx
  • From: Nico Coesel
• Re: 2 leg crystal on FPGA: Lattice vs Xilinx
  • From: Nico Coesel
• XUPV2P from digilentinc
  • From: johnzulu [at] yahoo . com
• Re: FPGA NTSC signal with 2 resistors and PWM
  • From: Antti
• Re: 2 leg crystal on FPGA: Lattice vs Xilinx
  • From: Antti
• Re: 2 leg crystal on FPGA: Lattice vs Xilinx
  • From: Antti
• Re: 2 leg crystal on FPGA: Lattice vs Xilinx
  • From: Hal Murray
• Re: 2 leg crystal on FPGA: Lattice vs Xilinx
  • From: Antti
• Re: 2 leg crystal on FPGA: Lattice vs Xilinx
  • From: Hal Murray
• Re: 2 leg crystal on FPGA: Lattice vs Xilinx
  • From: Phil Hays
• Re: 2 leg crystal on FPGA: Lattice vs Xilinx
  • From: vasile
• Re: FATAL ERROR ISE9.1i
  • From: andrea . pellegrini
• Re: 2 leg crystal on FPGA: Lattice vs Xilinx
  • From: Peter Alfke
• Re: FPGA NTSC signal with 2 resistors and PWM
  • From: Jecel
• Re: 2 leg crystal on FPGA: Lattice vs Xilinx
  • From: John Adair
• Re: job inquiry; entry/trainee FPGA/ASIC designer
  • From: John Adair
• Re: Never buy Altera!!!!
  • From: Matthew Hicks
• Re: Never buy Altera!!!!
  • From: Matthew Hicks
• [offtopic] job inquiry; entry/trainee FPGA/ASIC designer
  • From: theanonymous83
• Re: Bug in Synplify?
  • From: Andy
• Re: Low-level FPGA programming?
  • From: cs_posting
• Re: Never buy Altera!!!!
  • From: Jon Elson
• Re: Never buy Altera!!!!
  • From: Jon Elson
• Re: 2 leg crystal on FPGA: Lattice vs Xilinx
  • From: austin
• Re: Programming the ARM7 used to download our Xilinx FPGA
  • From: Hal Murray
• Re: Programming the ARM7 used to download our Xilinx FPGA
  • From: Sean Durkin
• Re: Never buy Altera!!!!
  • From: Hal Murray
• Re: Programming the ARM7 used to download our Xilinx FPGA
  • From: Antti
• Programming the ARM7 used to download our Xilinx FPGA
  • From: Dan K
• 2 leg crystal on FPGA: Lattice vs Xilinx
  • From: Antti
• Re: LVDS clock management
  • From: BobW
• Re: FPDP to PCIe
  • From: vasile
• LVDS clock management
  • From: vasile
• Re: FPGA NTSC signal with 2 resistors and PWM
  • From: Antti
• Re: FPGA NTSC signal with 2 resistors and PWM
  • From: Kevin Neilson
• Re: Bug in Synplify?
  • From: Andy
• Re: Bug in Synplify?
  • From: Ray Andraka
• Re: Never buy Altera!!!!
  • From: Ray Andraka
• Re: FPGA NTSC signal with 2 resistors and PWM
  • From: Antti
• Re: FPGA NTSC signal with 2 resistors and PWM
  • From: John_H
• Re: FPGA NTSC signal with 2 resistors and PWM
  • From: Antti
• Re: FPGA NTSC signal with 2 resistors and PWM
  • From: Gabor
• FPGA NTSC signal with 2 resistors and PWM
  • From: Antti
• Check it out:Very good online resources,tons of cool men and beautiful women eager for lovers....:
  • From: bull bruce
• Re: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?
  • From: Wei Wang
• Re: Never buy Altera!!!!
  • From: Martin Thompson
• Re: Low-level FPGA programming?
  • From: Andreas Ehliar
• Re: UCF Constraints: drive and slew
  • From: Pablo
• Re: Xilinx upgrade
  • From: pemiliv
• Re: Xilinx upgrade
  • From: svenand
• Re: Bug in Synplify?
  • From: Tommy Thorn
• Re: Bug in Synplify?
  • From: Thomas Stanka
• Re: Bug in Synplify?
  • From: Thomas Stanka
• Re: Never buy Altera!!!!
  • From: Tommy Thorn
• Re: Never buy Altera!!!!
  • From: Matthew Hicks
• Re: Never buy Altera!!!!
  • From: Mark McDougall
• Re: Never buy Altera!!!!
  • From: Mark McDougall
• Re: Never buy Altera!!!!
  • From: Jeff Cunningham
• Re: Xilinx upgrade
  • From: Jeff Cunningham
• Re: Basic questions about the Nios II.
  • From: Hal Murray
• Re: Xilinx upgrade
  • From: motty
• Re: Never buy Altera!!!!
  • From: Jon Elson
• PowerPC Simulation
  • From: motty
• Re: Never buy Altera!!!!
  • From: Jon Elson
• Re: Bug in Synplify?
  • From: Andy
• Xilinx upgrade
  • From: emrith
• Re: UCF Constraints: drive and slew
  • From: Gabor
• Re: Stratix GX
  • From: jon
• UCF Constraints: drive and slew
  • From: Pablo
• FPDP to PCIe
  • From: Sanka Piyaratna
• Re: Bug in Synplify?
  • From: John_H
• Re: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?
  • From: Gabor
• Re: Basic questions about the Nios II.
  • From: NickNitro
• Re: Basic questions about the Nios II.
  • From: Uncle Noah
• Re: Basic questions about the Nios II.
  • From: NickNitro
• Re: Basic questions about the Nios II.
  • From: Uncle Noah
• Re: Basic questions about the Nios II.
  • From: Uncle Noah
• Bug in Synplify?
  • From: Thomas Stanka
• Re: Basic questions about the Nios II.
  • From: NickNitro
• Re: Basic questions about the Nios II.
  • From: NickNitro
• Re: Basic questions about the Nios II.
  • From: Uncle Noah
• Basic questions about the Nios II.
  • From: NickNitro
• Re: Gated Clock Problems
  • From: Peter Alfke
• Re: Own soft-processor
  • From: Eric Smith
• Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
  • From: Eric Smith
• Re: Inferring wide adders comprising multiple DSP48s
  • From: Ray Andraka
• Re: Never buy Altera!!!!
  • From: cs_posting
• Re: Inferring wide adders comprising multiple DSP48s
  • From: John_H
• Re: Never buy Altera!!!!
  • From: Andy Peters
• Stratix GX
  • From: jon
• Inferring wide adders comprising multiple DSP48s
  • From: Kevin Neilson
• Re: partial reconfiguration, par error
  • From: Erik Anderson
• Re: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?
  • From: Wei Wang
• Re: Never buy Altera!!!!
  • From: fpgabuilder
• Re: Never buy Altera!!!!
  • From: Nico Coesel
• Re: Very basic clock questions.
  • From: fpgabuilder
• Altera PowerPlay Early Power Estimator Spreadsheet and MXCOMCT2.OCX
  • From: fpgabuilder
• Re: Never buy Altera!!!!
  • From: Mike Lewis
• Re: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?
  • From: Wei Wang
• Re: XST corrupts my state machine. Only disabling FSM encoding helps
  • From: John McCaskill
• Re: XST corrupts my state machine. Only disabling FSM encoding helps
  • From: heinerlitz@xxxxxxxxxxxxxx
• Re: XST corrupts my state machine. Only disabling FSM encoding helps
  • From: Joseph Samson
• XST corrupts my state machine. Only disabling FSM encoding helps
  • From: heinerlitz@xxxxxxxxxxxxxx
• Re: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?
  • From: Gabor
• Re: Never buy Altera!!!!
  • From: Jim Granville
• Re: Never buy Altera!!!!
  • From: Symon
• Re: Never buy Altera!!!!
  • From: Symon
• Re: Never buy Altera!!!!
  • From: Uwe Bonnes
• Re: Very basic clock questions.
  • From: Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
• Re: Never buy Altera!!!!
  • From: Hal Murray
• Re: Very basic clock questions.
  • From: NickNitro
• Re: Very basic clock questions.
  • From: David Spencer
• Very basic clock questions.
  • From: NickNitro
• Re: Never buy Altera!!!!
  • From: John_H
• Re: Never buy Altera!!!!
  • From: Hal Murray
• Re: Never buy Altera!!!!
  • From: Mark McDougall
• Re: Never buy Altera!!!!
  • From: Symon
• Re: Never buy Altera!!!!
  • From: Andy Peters
• Re: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?
  • From: Wei Wang
• Re: Never buy Altera!!!!
  • From: cs_posting
• Re: Never buy Altera!!!!
  • From: Nico Coesel
• Re: Own soft-processor
  • From: Hal Murray
• Re: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?
  • From: Gabor
• Re: Never buy Altera!!!!
  • From: Mike Treseler
• Re: Own soft-processor
  • From: Jon Beniston
• Re: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?
  • From: Weng Tianxiang
• Re: Own soft-processor
  • From: Uncle Noah
• Re: DRAM modules - RIMM, SODIMM,UDIMM..etc
  • From: Joseph Samson
• Own soft-processor
  • From: drop669
• Re: Gated Clock Problems
  • From: Allan Herriman
• Re: Never buy Altera!!!!
  • From: jinkeles
• How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?
  • From: Wei Wang
• Re: Verilog simple dual port memory with different input and output widths?
  • From: davew
• Re: Never buy Altera!!!!
  • From: Karl
• Re: Never buy Altera!!!!
  • From: comp.arch.fpga
• Re: Never buy Altera!!!!
  • From: cs_posting
• Re: Never buy Altera!!!!
  • From: Mike Treseler
• Never buy Altera!!!!
  • From: cs_posting
• Re: Gated Clock Problems
  • From: Symon
• Re: Automotive Electronic Control
  • From: Martin Thompson
• Variable Phase Shifting for VirtexII DCM
  • From: schirinboy
• Re: Automotive Electronic Control
  • From: Jonathan Bromley
• DRAM modules - RIMM, SODIMM,UDIMM..etc
  • From: sai
• Re: Automotive Electronic Control
  • From: Jonathan Bromley
• Re: Automotive Electronic Control
  • From: Martin Thompson
• Re: [ANN] FPGAOptim - Do you know where your slices are going...?
  • From: Martin Thompson
• Check it out:Two best way to get friends worldwide
  • From: pegclark
• Re: Gated Clock Problems
  • From: Symon
• Re: Verilog simple dual port memory with different input and output widths?
  • From: Kevin Neilson
• Re: [ANN] FPGAOptim - Do you know where your slices are going...?
  • From: MM
• Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
  • From: Jim Granville
• Re: Configuring Impact on any version of linux
  • From: MM
• Automotive Electronic Control
  • From: icegray
• Re: Gated Clock Problems
  • From: Symon
• Re: Gated Clock Problems
  • From: Jon Elson
• Re: Gated Clock Problems
  • From: Jon Elson
• Re: Gated Clock Problems
  • From: Jon Elson
• Re: Gated Clock Problems
  • From: Mike Lewis
• Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
  • From: Antti
• partial reconfiguration, par error
  • From: gilbert1219com
• Re: CRC calculation of Virtex 4 bitstream
  • From: lembke . stefan
• [ANN] FPGAOptim - Do you know where your slices are going...?
  • From: Martin Thompson
• BRAM bytewide write enable problem
  • From: bharat_in
• Re: help! ACTEL PROASIC PLUS clock buffer
  • From: Thomas Stanka
• Re: help! ACTEL PROASIC PLUS clock buffer
  • From: Thomas Stanka
• Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
  • From: Eric Smith
• Re: Gated Clock Problems
  • From: Eric Smith
• Re: Gated Clock Problems
  • From: Uwe Bonnes
• Re: Gated Clock Problems
  • From: Weng Tianxiang
• Re: Gated Clock Problems
  • From: Marlboro
• Xilinx GTP based serial link
  • From: Sanka Piyaratna
• Re: Gated Clock Problems
  • From: vasile
• Any advice on Steve Kilts' "Advanced FPGA Design: Architecture, Implementation, and Optimization" ?
  • From: James Peters
• Re: Looking for fast AES cores with low latency
  • From: glen herrmannsfeldt
• Re: CRC calculation of Virtex 4 bitstream
  • From: Mike Treseler
• CRC calculation of Virtex 4 bitstream
  • From: lembke . stefan
• Re: Gated Clock Problems
  • From: mk
• Xilinx Microblaze EDK and Virtex5/LXT TEMAC core?
  • From: Helpme
• DDR RAM timing contraints
  • From: pwie42
• Re: Configuring Impact on any version of linux
  • From: svenand
• Configuring Impact on any version of linux
  • From: Ankit
• Re: Looking for fast AES cores with low latency
  • From: Allan Herriman
• Re: Gated Clock Problems
  • From: Hal Murray
• Re: Gated Clock Problems
  • From: Stef
• Re: Gated Clock Problems
  • From: Gabor
• Re: baord for learning softcore processor
  • From: svenand
• Re: proasic plus. actel
  • From: dscolson@xxxxxxx
• Re: Gated Clock Problems
  • From: Symon
• Re: help! ACTEL PROASIC PLUS clock buffer
  • From: Mike Treseler
• Re: Looking for fast AES cores with low latency
  • From: glen herrmannsfeldt
• Re: Gated Clock Problems
  • From: glen herrmannsfeldt
• Re: Clock boundary crossing
  • From: glen herrmannsfeldt
• Re: baord for learning softcore processor
  • From: John_H
• baord for learning softcore processor
  • From: fp
• Enterpoint Web Site
  • From: John Adair
• Re: help! ACTEL PROASIC PLUS clock buffer
  • From: merche
• Using PlanAhead for Partial Reconfiguration
  • From: gilbert1219com
• Re: DMA scatter gather with PLB bus?
  • From: cesarp
• Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
  • From: Manny
• Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
  • From: Antti
• Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
  • From: Manny
• Re: how interfacing of cpld and cpu done?
  • From: Antti
• Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
  • From: Antti
• how interfacing of cpld and cpu done?
  • From: nanaware_amit
• Re: help! ACTEL PROASIC PLUS clock buffer
  • From: Thomas Stanka
• Re: Is it possible to perform gate level simulation on a design without a reset?
  • From: Ray Andraka
• Re: hardware software codesign
  • From: John Retta
• Re: Clock boundary crossing
  • From: Alan Nishioka
• Re: Comparing Adder synthesis techniques
  • From: John_H
• Re: hardware software codesign
  • From: Hal Murray
• hardware software codesign
  • From: gks . 1981
• Re: Free downloadable PDF graph paper.
  • From: Guenter
• Re: Clock boundary crossing
  • From: Hal Murray
• Re: Comparing Adder synthesis techniques
  • From: Mike Treseler
• Re: DMA scatter gather with PLB bus?
  • From: Jeff Cunningham
• Re: Gated Clock Problems
  • From: Hal Murray
• Re: Comparing Adder synthesis techniques
  • From: David R Brooks
• Re: Gated Clock Problems
  • From: Hal Murray
• Comparing Adder synthesis techniques
  • From: Joseph
• DMA scatter gather with PLB bus?
  • From: cesarp
• Re: Clock boundary crossing
  • From: Mike Treseler
• Re: Gated Clock Problems
  • From: mk
• Re: Gated Clock Problems
  • From: Symon
• Re: Gated Clock Problems
  • From: Stef
• Re: Is it possible for two wires to share the same FPGA pin?
  • From: mk
• Re: Gated Clock Problems
  • From: Symon
• Re: Looking for fast AES cores with low latency
  • From: Allan Herriman
• Is it possible for two wires to share the same FPGA pin?
  • From: Wei Wang
• Re: Gated Clock Problems
  • From: Mike Lewis
• Re: Gated Clock Problems
  • From: vasile
• Re: Virtex-4 SELECT MAP configuration
  • From: jerzy.gbur@xxxxxxxxx
• proasic plus. actel
  • From: merche
• Re: help! ACTEL PROASIC PLUS clock buffer
  • From: merche
• Multi-cycle paths in VHDL libraries
  • From: GKnittel
• Re: Clock boundary crossing
  • From: Hal Murray
• Re: Looking for fast AES cores with low latency
  • From: backhus
• Re: help! ACTEL PROASIC PLUS clock buffer
  • From: Thomas Stanka
• Re: Gated Clock Problems
  • From: Hal Murray
• Gated Clock Problems
  • From: Berk Birand
• Re: Looking for fast AES cores with low latency
  • From: IDDLife
• Re: FPGA history
  • From: Hal Murray
• Re: FPGA history
  • From: Uwe Bonnes
• Re: Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL
  • From: Andy Peters
• Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
  • From: Jeff Cunningham
• help! ACTEL PROASIC PLUS clock buffer
  • From: merche
• Re: FPGA history
  • From: comp.arch.fpga
• Re: Looking for fast AES cores with low latency
  • From: Allan Herriman
• Re: FPGA history
  • From: Rafael Deliano
• Re: global clock on virtex5 question
  • From: vasile
• Re: FPGA history
  • From: Sven Heithecker
• FPGA history
  • From: Sven Heithecker
• Re: Population Count circuit
  • From: Symon
• Re: Looking for fast AES cores with low latency
  • From: backhus
• Re: how to bidirectional signal in xilinx EDK tool ?
  • From: lionheart70
• Re: Tristate bus on spartan FPGA
  • From: aravind
• Re: Looking for fast AES cores with low latency
  • From: IDDLife
• Re: Peripheral Trouble!
  • From: John McCaskill
• Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
  • From: Jim Granville
• Re: Altera / Lattice / Xilinx CPLDs ?
  • From: Jon Elson
• Re: Altera / Lattice / Xilinx CPLDs ?
  • From: Jim Granville
• Re: Altera / Lattice / Xilinx CPLDs ?
  • From: Jim Granville
• Re: Tristate bus on spartan FPGA
  • From: glen herrmannsfeldt
• Re: Tristate bus on spartan FPGA
  • From: Mike Treseler
• Verilog simple dual port memory with different input and output widths?
  • From: davew
• Re: Peripheral Trouble!
  • From: MJ Pearson
• Re: Symbolic names for pll derived clocks in SDC file? (quartus)
  • From: Topi Rinkinen
• Re: Looking for fast AES cores with low latency
  • From: Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
• Re: global clock on virtex5 question
  • From: Ed McGettigan
• Looking for fast AES cores with low latency
  • From: Allan Herriman
• Re: Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL
  • From: fastgreen2000
• Re: Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL
  • From: fastgreen2000
• Re: Slice equation in bitstream
  • From: Symon
• Re: Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL
  • From: Martin Thompson
• Re: Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL
  • From: Gabor
• Re: Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL
  • From: Gabor
• Re: Tristate bus on spartan FPGA
  • From: Mike Lewis
• Re: Unexplained behavior with DDR2 controller on Xilinx V5
  • From: Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
• Data-side BRAM
  • From: xenix
• Re: Tristate bus on spartan FPGA
  • From: Jon Beniston
• Re: Tristate bus on spartan FPGA
  • From: Amontec, Larry
• Re: Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL
  • From: Martin Thompson
• Re: Slice equation in bitstream
  • From: lembke . stefan
• Re: Unexplained behavior with DDR2 controller on Xilinx V5
  • From: jacobusn@xxxxxxxxxx
• Re: Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL
  • From: Laurent Pinchart
• Re: Tristate bus on spartan FPGA
  • From: Maki
• Re: Altera / Lattice / Xilinx CPLDs ?
  • From: Uwe Bonnes
• Re: Tristate bus on spartan FPGA
  • From: RCIngham
• Tristate bus on spartan FPGA
  • From: aravind
• Re: Unexplained behavior with DDR2 controller on Xilinx V5
  • From: Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
• Re: Altera / Lattice / Xilinx CPLDs ?
  • From: vasile
• Re: global clock on virtex5 question
  • From: vasile
• Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL
  • From: fastgreen2000
• Virtex-4 SELECT MAP configuration
  • From: Pasacco
• Re: YARDstick - custom processor development toolset
  • From: Uncle Noah
• Re: Altera / Lattice / Xilinx CPLDs ?
  • From: John_H
• Re: Physical Design Contribution to FPGA/CPLD success
  • From: glen herrmannsfeldt
• Re: Altera / Lattice / Xilinx CPLDs ?
  • From: Gabor
• Re: Altera / Lattice / Xilinx CPLDs ?
  • From: Uwe Bonnes
• Re: Unexplained behavior with DDR2 controller on Xilinx V5
  • From: Brad Smallridge
• Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
  • From: Tobias Weingartner
• Re: Altera / Lattice / Xilinx CPLDs ?
  • From: ghelbig
• Re: Altera / Lattice / Xilinx CPLDs ?
  • From: John_H
• Re: MicroBlaze Tutorial
  • From: svenand
• Directing data to DDR
  • From: S
• Re: Altera / Lattice / Xilinx CPLDs ?
  • From: austin
• Re: global clock on virtex5 question
  • From: Ed McGettigan
• Altera / Lattice / Xilinx CPLDs ?
  • From: Amontec, Larry
• Re: Beginner Advice (Languages, tools etc.)
  • From: Bob Perlman
• Re: VCCAUX too high on a Spartan 3 design
  • From: Dan K
• Re: overloading ' operators in VHDL
  • From: RCIngham
• Re: clock skew problems
  • From: Gabor
• Re: Virtex-4 PCB design
  • From: Gabor
• Re: post translate and post PAR problems with XST and Modelsim
  • From: Gabor
• ECP2/M und Serdes
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• Re: load/read/ commands assembly PowerPC. Help Needed!
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• Re: ANNC: New Boundary-Scan Software
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• Re: VCCAUX too high on a Spartan 3 design
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• DDR Simulation via MIG
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• VCCAUX too high on a Spartan 3 design
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• Re: Problem locking a DCM driven by FX output of another DCM
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• ANNC: New Boundary-Scan Software
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• Re: Problem locking a DCM driven by FX output of another DCM
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• Re: Problem locking a DCM driven by FX output of another DCM
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• Re: Problem locking a DCM driven by FX output of another DCM
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• Re: load/read/ commands assembly PowerPC. Help Needed!
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• Re: Problem locking a DCM driven by FX output of another DCM
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• Re: Free downloadable PDF graph paper.
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• Free downloadable PDF graph paper.
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• Re: Is it possible to perform gate level simulation on a design without a reset?
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• Is it possible to perform gate level simulation on a design without a reset?
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• Re: PCB Impedance Control
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• Re: ?Nios II?How Can I Find Out These Functions ?
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• Re: PCB Impedance Control
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• Re: How to deal with the tempary coefficient in the FPGA design
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• Re: How to deal with the tempary coefficient in the FPGA design
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• Re: How to deal with the tempary coefficient in the FPGA design
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• Re: PCB Impedance Control
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• Re: PCB Impedance Control
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• Re: FPGA CPU
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• Re: ¡¾Nios II¡¿How Can I Find Out These Functions £¿
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• 【Nios II】How Can I Find Out These Functions ？
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• Re: PCB Impedance Control
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• Re: PCB Impedance Control
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• Re: Multiple CPLDs on a PCB.
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• How to deal with the tempary coefficient in the FPGA design
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• Re: Spartan3E and DDR termination
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• Re: FPGA CPU
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• Re: Multiple CPLDs on a PCB.
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• Re: Multiple CPLDs on a PCB.
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• Re: PCB Impedance Control
  • From: glen herrmannsfeldt
• Re: FPGA CPU
  • From: fpga_toys
• Re: PCB Impedance Control
  • From: vasile
• vnavigator problem
  • From: kkoorndyk
• Re: Multiple CPLDs on a PCB.
  • From: Jim Granville
• Re: PCB Impedance Control
  • From: vasile
• Re: Spartan3E and DDR termination
  • From: vasile
• Re: ERROR:NgdBuild:604 with user ipcore
  • From: Paulo Dutra
• Re: FPGA CPU
  • From: fpga_toys
• Multiple CPLDs on a PCB.
  • From: NickNitro
• Actel Designer - Specifying multicycle path constraints (via .sdc file) when using synchronous clock enables
  • From: David
• Re: PCB Impedance Control
  • From: John Larkin
• Re: PCB Impedance Control
  • From: John Larkin
• Re: ERROR:NgdBuild:604 with user ipcore
  • From: L. Schreiber
• Re: ERROR:NgdBuild:604 with user ipcore
  • From: Gabor
• ERROR:NgdBuild:604 with user ipcore
  • From: L. Schreiber
• Import Xilinx SDK Project in Wind River Workbench
  • From: LilacSkin
• ERROR:NgdBuild:604 with user ipcore
  • From: L. Schreiber
• Re: PCB Impedance Control
  • From: Symon
• Re: FPGA CPU
  • From: Göran Bilski
• Re: PCB Impedance Control
  • From: kayrock66
• Re: FPGA CPU
  • From: glen herrmannsfeldt
• Re: opb_timer interrupt self test problem
  • From: DoPeti
• Re: opb_timer interrupt self test problem
  • From: benradu
• Actel IGLOO FPGA has lower power consumption then Xilinx Coolrunner-II CPLD?
  • From: ikogan
• Re: V5 Configuration via SPI
  • From: Sean Durkin
• Re: Low-level FPGA programming?
  • From: Jon Beniston
• Re: Low-level FPGA programming?
  • From: austin
• Re: V5 Configuration via SPI
  • From: austin
• Help on OCM BRAM intercafe and assembly code
  • From: xenix
• Help on ocm
  • From: xenix
• Re: V5 Configuration via SPI
  • From: Sean Durkin
• Re: FPGA CPU
  • From: Andreas Ehliar
• Re: Low-level FPGA programming?
  • From: RedskullDC
• Re: FPGA CPU
  • From: Andreas Ehliar
• Re: Low-level FPGA programming?
  • From: Andreas Ehliar
• Re: Low-level FPGA programming?
  • From: drop669
• Re: Spartan 3E - Readback via JTAG
  • From: Uwe Bonnes
• Re: FPGA CPU
  • From: James Harris
• Re: VHDL core to read/write to Bram_Block.
  • From: Pablo
• Re: Die size, pitch size?
  • From: j . d . morrison
• Re: How to add additional FSL interface to customized IP?
  • From: Göran Bilski
• Re: An FPGA startup is seeking testcase from potential customers
  • From: j . d . morrison
• Re: Low-level FPGA programming?
  • From: Paul Leventis
• Re: How Can I define the pio inputs as a interrupt?
  • From: hezhikuan2007
• GTKWave 3.1.0 for win32
  • From: mk
• Re: [Nios II] How Can I define the pio inputs as a interrupt?
  • From: Mark McDougall
• [Nios II] How Can I define the pio inputs as a interrupt?
  • From: hezhikuan2007
• Low-level FPGA programming?
  • From: drop669
• Cannot pass par in tcl, Xilinx webpack 9.1.
  • From: fl
• Re: V5 Configuration via SPI
  • From: John Larkin
• Re: FPGA CPU
  • From: Andreas Ehliar
• FPGA CPU
  • From: James Harris
• Beginning FPGA programming
  • From: James Harris
• Re: V5 Configuration via SPI
  • From: austin
• opb_timer interrupt self test problem
  • From: dormanpeter1
• V5 Configuration via SPI
  • From: Sean Durkin
• Re: PCB Impedance Control
  • From: John Larkin
• Re: PCB Impedance Control
  • From: John Larkin
• Re: PCB Impedance Control
  • From: Hal Murray
• Re: PCB Impedance Control
  • From: Hal Murray
• Re: PCIe question
  • From: John Adair
• Re: Spartan 3E starter kit (Rev.D) modification : 3E500 -> 3E1200
  • From: John Adair
• Re: PCB Layers
  • From: Symon
• Re: Spartan3E and DDR termination
  • From: Guru
• Re: PCB Layers
  • From: Symon
• Re: PCB Impedance Control
  • From: Symon
• Re: flip-flop enable
  • From: Ralf Hildebrandt
• flip-flop enable
  • From: al . basili
• Re: Strange behaviour of a design
  • From: Kunal
• Re: Strange behaviour of a design
  • From: Kunal
• Re: Chip Designing made Easy
  • From: Antti
• Re: Memory bandwidth of the 3A kit
  • From: Antti
• Re: PCB Layers
  • From: KJ
• Re: Partial reconfiguration using ICAP
  • From: Sean Durkin
• Re: comparison with embedded processor
  • From: Daniel S.
• Re: PCB Impedance Control
  • From: John Larkin
• Re: PCB Layers
  • From: maxascent
• Interesting FPGA/JTAG project.
  • From: Symon
• Re: PCB Layers
  • From: Symon
• Re: Is it possible to make bit files generated by Xilinx ISE readable?
  • From: glen herrmannsfeldt
• Re: Newbie with ISE 9_2_02i_lin gets error : Process "Translate" failed
  • From: Bob Smith
• Re: Xilinx ML40x Mouse VHDL Wanted
  • From: ghelbig
• Re: PCB Impedance Control
  • From: PeteS
• Re: PLL Power and m/n ratio
  • From: fpgabuilder
• Re: An FPGA startup is seeking testcase from potential customers
  • From: fpgabuilder
• Re: Die size, pitch size?
  • From: Jim Granville
• Re: Die size, pitch size?
  • From: John_H
• Re: Die size, pitch size?
  • From: Peter Alfke
• How to add additional FSL interface to customized IP?
  • From: David Chen
• Re: Die size, pitch size?
  • From: Pasacco

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