comp.arch.fpga

• Date Index

• Planning to switch to FPGA domain, any advice would be highly appreciated, To: Kshitij Arora <
• Walking 1's, Walters
  • Re: Walking 1's, PeteS
    • Re: Walking 1's, Jonathan Bromley
    • Re: Walking 1's, MikeShepherd564
• www.fpga-games.com website died?, Antti
• please help me for vhdl code of temprature controller, nanaware_amit
  • Re: please help me for vhdl code of temprature controller, Nicolas Matringe
• XUPV2P from digilentinc, johnzulu [at] yahoo . com
  • Re: XUPV2P from digilentinc, stephen.craven@xxxxxxxxx
    • Re: XUPV2P from digilentinc, johnzulu [at] yahoo . com
      • Re: XUPV2P from digilentinc, emu
      • Re: XUPV2P from digilentinc, John_H
    • Re: XUPV2P from digilentinc, Brian Drummond
      • Re: XUPV2P from digilentinc, johnzulu [at] yahoo . com
      • Re: XUPV2P from digilentinc, vasile
• [offtopic] job inquiry; entry/trainee FPGA/ASIC designer, theanonymous83
  • Re: job inquiry; entry/trainee FPGA/ASIC designer, John Adair
  • Re: [offtopic] job inquiry; entry/trainee FPGA/ASIC designer, Symon
    • Re: job inquiry; entry/trainee FPGA/ASIC designer, theanonymous83
      • Re: job inquiry; entry/trainee FPGA/ASIC designer, Symon
  • Re: job inquiry; entry/trainee FPGA/ASIC designer, John McCaskill
• Programming the ARM7 used to download our Xilinx FPGA, Dan K
  • Re: Programming the ARM7 used to download our Xilinx FPGA, Antti
  • Re: Programming the ARM7 used to download our Xilinx FPGA, Sean Durkin
  • Re: Programming the ARM7 used to download our Xilinx FPGA, Hal Murray
• 2 leg crystal on FPGA: Lattice vs Xilinx, Antti
  • Re: 2 leg crystal on FPGA: Lattice vs Xilinx, austin
    • Re: 2 leg crystal on FPGA: Lattice vs Xilinx, John Adair
      • Re: 2 leg crystal on FPGA: Lattice vs Xilinx, Peter Alfke
      • Re: 2 leg crystal on FPGA: Lattice vs Xilinx, Antti
      • Re: 2 leg crystal on FPGA: Lattice vs Xilinx, Nico Coesel
      • Re: 2 leg crystal on FPGA: Lattice vs Xilinx, John_H
      • Re: 2 leg crystal on FPGA: Lattice vs Xilinx, Nico Coesel
      • Re: 2 leg crystal on FPGA: Lattice vs Xilinx, johnp
      • Re: 2 leg crystal on FPGA: Lattice vs Xilinx, Ray Andraka
      • Re: 2 leg crystal on FPGA: Lattice vs Xilinx, Antti
      • Re: 2 leg crystal on FPGA: Lattice vs Xilinx, Antti
      • Re: 2 leg crystal on FPGA: Lattice vs Xilinx, Hal Murray
      • Re: 2 leg crystal on FPGA: Lattice vs Xilinx, Antti
      • Re: 2 leg crystal on FPGA: Lattice vs Xilinx, KJ
      • Re: 2 leg crystal on FPGA: Lattice vs Xilinx, Antti
      • Re: 2 leg crystal on FPGA: Lattice vs Xilinx, Ray Andraka
  • Re: 2 leg crystal on FPGA: Lattice vs Xilinx, vasile
    • Re: 2 leg crystal on FPGA: Lattice vs Xilinx, Phil Hays
      • Re: 2 leg crystal on FPGA: Lattice vs Xilinx, Hal Murray
      • Re: 2 leg crystal on FPGA: Lattice vs Xilinx, Nico Coesel
      • Re: 2 leg crystal on FPGA: Lattice vs Xilinx, John Adair
      • Re: 2 leg crystal on FPGA: Lattice vs Xilinx, Phil Hays
• LVDS clock management, vasile
  • Re: LVDS clock management, BobW
• FPGA NTSC signal with 2 resistors and PWM, Antti
  • Re: FPGA NTSC signal with 2 resistors and PWM, Gabor
    • Re: FPGA NTSC signal with 2 resistors and PWM, Antti
      • Re: FPGA NTSC signal with 2 resistors and PWM, John_H
      • Re: FPGA NTSC signal with 2 resistors and PWM, Antti
  • Re: FPGA NTSC signal with 2 resistors and PWM, Kevin Neilson
    • Re: FPGA NTSC signal with 2 resistors and PWM, Antti
      • Re: FPGA NTSC signal with 2 resistors and PWM, Jecel
      • Re: FPGA NTSC signal with 2 resistors and PWM, Antti
      • Re: FPGA NTSC signal with 2 resistors and PWM, Jecel
• Check it out:Very good online resources,tons of cool men and beautiful women eager for lovers....:, bull bruce
• PowerPC Simulation, motty
  • Re: PowerPC Simulation, Ken Ryan
• Xilinx upgrade, emrith
  • Re: Xilinx upgrade, motty
  • Re: Xilinx upgrade, Jeff Cunningham
  • Re: Xilinx upgrade, svenand
    • Re: Xilinx upgrade, pemiliv
• UCF Constraints: drive and slew, Pablo
  • Re: UCF Constraints: drive and slew, Gabor
    • Re: UCF Constraints: drive and slew, Pablo
• FPDP to PCIe, Sanka Piyaratna
  • Re: FPDP to PCIe, vasile
• Bug in Synplify?, Thomas Stanka
  • Re: Bug in Synplify?, John_H
  • Re: Bug in Synplify?, Andy
    • Re: Bug in Synplify?, Thomas Stanka
    • Re: Bug in Synplify?, Thomas Stanka
      • Re: Bug in Synplify?, Tommy Thorn
      • Re: Bug in Synplify?, Andy
      • Re: Bug in Synplify?, Ray Andraka
      • Re: Bug in Synplify?, Andy
• Basic questions about the Nios II., NickNitro
  • Re: Basic questions about the Nios II., Uncle Noah
    • Re: Basic questions about the Nios II., NickNitro
      • Re: Basic questions about the Nios II., NickNitro
      • Re: Basic questions about the Nios II., Uncle Noah
      • Re: Basic questions about the Nios II., NickNitro
      • Re: Basic questions about the Nios II., Uncle Noah
      • Re: Basic questions about the Nios II., NickNitro
      • Re: Basic questions about the Nios II., Uncle Noah
      • Re: Basic questions about the Nios II., Hal Murray
• Stratix GX, jon
  • Re: Stratix GX, jon
• Inferring wide adders comprising multiple DSP48s, Kevin Neilson
  • Re: Inferring wide adders comprising multiple DSP48s, John_H
  • Re: Inferring wide adders comprising multiple DSP48s, Ray Andraka
• Altera PowerPlay Early Power Estimator Spreadsheet and MXCOMCT2.OCX, fpgabuilder
• XST corrupts my state machine. Only disabling FSM encoding helps, heinerlitz@xxxxxxxxxxxxxx
  • Re: XST corrupts my state machine. Only disabling FSM encoding helps, Joseph Samson
    • Re: XST corrupts my state machine. Only disabling FSM encoding helps, heinerlitz@xxxxxxxxxxxxxx
  • Re: XST corrupts my state machine. Only disabling FSM encoding helps, John McCaskill
  • Re: XST corrupts my state machine. Only disabling FSM encoding helps, Helpme
• Very basic clock questions., NickNitro
  • Re: Very basic clock questions., David Spencer
    • Re: Very basic clock questions., NickNitro
  • Re: Very basic clock questions., Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
    • Re: Very basic clock questions., fpgabuilder
• Own soft-processor, drop669
  • Re: Own soft-processor, Uncle Noah
  • Re: Own soft-processor, Jon Beniston
  • Re: Own soft-processor, Hal Murray
  • Re: Own soft-processor, Eric Smith
  • Re: Own soft-processor, Jarek Rozanski
  • Re: Own soft-processor, Nicolas Matringe
    • Re: Own soft-processor, emu
    • Re: Own soft-processor, sdf
      • Re: Own soft-processor, Tommy Thorn
    • Re: Own soft-processor, Andrew Burnside
• How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?, Wei Wang
  • Re: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?, Weng Tianxiang
    • Re: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?, Gabor
      • Re: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?, Wei Wang
      • Re: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?, Gabor
      • Re: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?, Wei Wang
      • Re: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?, Wei Wang
      • Re: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?, Gabor
      • Re: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?, Wei Wang
• Never buy Altera!!!!, cs_posting
  • Re: Never buy Altera!!!!, Mike Treseler
    • Re: Never buy Altera!!!!, cs_posting
  • Re: Never buy Altera!!!!, comp.arch.fpga
  • Re: Never buy Altera!!!!, Karl
  • Re: Never buy Altera!!!!, jinkeles
    • Re: Never buy Altera!!!!, Mike Treseler
    • Re: Never buy Altera!!!!, Nico Coesel
    • Re: Never buy Altera!!!!, cs_posting
    • Re: Never buy Altera!!!!, Andy Peters
      • Re: Never buy Altera!!!!, Symon
      • Re: Never buy Altera!!!!, Mark McDougall
      • Re: Never buy Altera!!!!, John_H
      • Re: Never buy Altera!!!!, Hal Murray
      • Re: Never buy Altera!!!!, fpgabuilder
      • Re: Never buy Altera!!!!, Mark McDougall
      • Re: Never buy Altera!!!!, Jon Elson
      • Re: Never buy Altera!!!!, Symon
      • Re: Never buy Altera!!!!, Jim Granville
      • Re: Never buy Altera!!!!, Mark McDougall
      • Re: Never buy Altera!!!!, Hal Murray
      • Re: Never buy Altera!!!!, Symon
      • Re: Never buy Altera!!!!, Hal Murray
      • Re: Never buy Altera!!!!, Andy Peters
      • Re: Never buy Altera!!!!, Nico Coesel
      • Re: Never buy Altera!!!!, Uwe Bonnes
      • Re: Never buy Altera!!!!, Mike Lewis
      • Re: Never buy Altera!!!!, cs_posting
      • Re: Never buy Altera!!!!, Jon Elson
      • Re: Never buy Altera!!!!, Jeff Cunningham
      • Re: Never buy Altera!!!!, Matthew Hicks
      • Re: Never buy Altera!!!!, Tommy Thorn
      • Re: Never buy Altera!!!!, Martin Thompson
      • Re: Never buy Altera!!!!, Jon Elson
      • Re: Never buy Altera!!!!, Ray Andraka
      • Re: Never buy Altera!!!!, Jon Elson
      • Re: Never buy Altera!!!!, Matthew Hicks
      • Re: Never buy Altera!!!!, Matthew Hicks
      • Re: Never buy Altera!!!!, Gabor
• Variable Phase Shifting for VirtexII DCM, schirinboy
• DRAM modules - RIMM, SODIMM,UDIMM..etc, sai
  • Re: DRAM modules - RIMM, SODIMM,UDIMM..etc, Joseph Samson
• Check it out:Two best way to get friends worldwide, pegclark
• Automotive Electronic Control, icegray
  • Re: Automotive Electronic Control, Martin Thompson
    • Re: Automotive Electronic Control, Jonathan Bromley
      • Re: Automotive Electronic Control, Martin Thompson
  • Re: Automotive Electronic Control, Jonathan Bromley
• partial reconfiguration, par error, gilbert1219com
  • Re: partial reconfiguration, par error, Erik Anderson
• [ANN] FPGAOptim - Do you know where your slices are going...?, Martin Thompson
  • Re: [ANN] FPGAOptim - Do you know where your slices are going...?, MM
    • Re: [ANN] FPGAOptim - Do you know where your slices are going...?, Martin Thompson
• BRAM bytewide write enable problem, bharat_in
• Xilinx GTP based serial link, Sanka Piyaratna
• Any advice on Steve Kilts' "Advanced FPGA Design: Architecture, Implementation, and Optimization" ?, James Peters
• CRC calculation of Virtex 4 bitstream, lembke . stefan
  • Re: CRC calculation of Virtex 4 bitstream, Mike Treseler
    • Re: CRC calculation of Virtex 4 bitstream, lembke . stefan
• Xilinx Microblaze EDK and Virtex5/LXT TEMAC core?, Helpme
• DDR RAM timing contraints, pwie42
• Configuring Impact on any version of linux, Ankit
  • Re: Configuring Impact on any version of linux, svenand
  • Re: Configuring Impact on any version of linux, MM
• baord for learning softcore processor, fp
  • Re: baord for learning softcore processor, John_H
    • Re: baord for learning softcore processor, svenand
• Enterpoint Web Site, John Adair
• Using PlanAhead for Partial Reconfiguration, gilbert1219com
• Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!, Antti
  • Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!, Manny
    • Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!, Antti
      • Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!, Manny
  • Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!, Eric Smith
    • Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!, Antti
      • Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!, Jim Granville
      • Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!, Eric Smith
• how interfacing of cpld and cpu done?, nanaware_amit
  • Re: how interfacing of cpld and cpu done?, Antti
• hardware software codesign, gks . 1981
  • Re: hardware software codesign, Hal Murray
  • Re: hardware software codesign, John Retta
• Comparing Adder synthesis techniques, Joseph
  • Re: Comparing Adder synthesis techniques, David R Brooks
  • Re: Comparing Adder synthesis techniques, Mike Treseler
  • Re: Comparing Adder synthesis techniques, John_H
• DMA scatter gather with PLB bus?, cesarp
  • Re: DMA scatter gather with PLB bus?, Jeff Cunningham
    • Re: DMA scatter gather with PLB bus?, cesarp
• Is it possible for two wires to share the same FPGA pin?, Wei Wang
  • Re: Is it possible for two wires to share the same FPGA pin?, mk
• proasic plus. actel, merche
  • Re: proasic plus. actel, dscolson@xxxxxxx
• Multi-cycle paths in VHDL libraries, GKnittel
• Gated Clock Problems, Berk Birand
  • Re: Gated Clock Problems, Hal Murray
    • Re: Gated Clock Problems, Jon Elson
  • Re: Gated Clock Problems, vasile
    • Re: Gated Clock Problems, Mike Lewis
      • Re: Gated Clock Problems, Symon
      • Re: Gated Clock Problems, Stef
      • Re: Gated Clock Problems, Symon
      • Re: Gated Clock Problems, mk
      • Re: Gated Clock Problems, Hal Murray
      • Re: Gated Clock Problems, Stef
      • Re: Gated Clock Problems, Hal Murray
      • Re: Gated Clock Problems, mk
      • Re: Gated Clock Problems, Jon Elson
      • Re: Gated Clock Problems, Symon
      • Re: Gated Clock Problems, Symon
      • Re: Gated Clock Problems, Allan Herriman
      • Re: Gated Clock Problems, glen herrmannsfeldt
      • Re: Gated Clock Problems, Symon
      • Re: Gated Clock Problems, Gabor
      • Re: Gated Clock Problems, Hal Murray
      • Re: Gated Clock Problems, vasile
      • Re: Gated Clock Problems, Marlboro
      • Re: Gated Clock Problems, Uwe Bonnes
      • Re: Gated Clock Problems, Weng Tianxiang
      • Re: Gated Clock Problems, Eric Smith
      • Re: Gated Clock Problems, Mike Lewis
      • Re: Gated Clock Problems, Symon
    • Re: Gated Clock Problems, Jon Elson
      • Re: Gated Clock Problems, Peter Alfke
• help! ACTEL PROASIC PLUS clock buffer, merche
  • Re: help! ACTEL PROASIC PLUS clock buffer, Thomas Stanka
    • Re: help! ACTEL PROASIC PLUS clock buffer, merche
      • Re: help! ACTEL PROASIC PLUS clock buffer, Thomas Stanka
      • Re: help! ACTEL PROASIC PLUS clock buffer, merche
      • Re: help! ACTEL PROASIC PLUS clock buffer, Mike Treseler
      • Re: help! ACTEL PROASIC PLUS clock buffer, Thomas Stanka
      • Re: help! ACTEL PROASIC PLUS clock buffer, Thomas Stanka
• FPGA history, Sven Heithecker
  • Re: FPGA history, Sven Heithecker
  • Re: FPGA history, Rafael Deliano
    • Re: FPGA history, Hal Murray
  • Re: FPGA history, comp.arch.fpga
  • Re: FPGA history, Uwe Bonnes
• Re: Population Count circuit, Symon
• Re: how to bidirectional signal in xilinx EDK tool ?, lionheart70
• Verilog simple dual port memory with different input and output widths?, davew
  • Re: Verilog simple dual port memory with different input and output widths?, Kevin Neilson
    • Re: Verilog simple dual port memory with different input and output widths?, davew
• Re: Symbolic names for pll derived clocks in SDC file? (quartus), Topi Rinkinen
• Looking for fast AES cores with low latency, Allan Herriman
  • Re: Looking for fast AES cores with low latency, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
    • Re: Looking for fast AES cores with low latency, IDDLife
  • Re: Looking for fast AES cores with low latency, backhus
  • Re: Looking for fast AES cores with low latency, Allan Herriman
    • Re: Looking for fast AES cores with low latency, IDDLife
    • Re: Looking for fast AES cores with low latency, backhus
      • Re: Looking for fast AES cores with low latency, Allan Herriman
      • Re: Looking for fast AES cores with low latency, glen herrmannsfeldt
      • Re: Looking for fast AES cores with low latency, Allan Herriman
      • Re: Looking for fast AES cores with low latency, glen herrmannsfeldt
• Data-side BRAM, xenix
• Re: Slice equation in bitstream, lembke . stefan
  • Re: Slice equation in bitstream, Symon
• Tristate bus on spartan FPGA, aravind
  • Re: Tristate bus on spartan FPGA, RCIngham
    • Re: Tristate bus on spartan FPGA, Maki
      • Re: Tristate bus on spartan FPGA, Amontec, Larry
      • Re: Tristate bus on spartan FPGA, glen herrmannsfeldt
      • Re: Tristate bus on spartan FPGA, Mike Treseler
  • Re: Tristate bus on spartan FPGA, Jon Beniston
    • Re: Tristate bus on spartan FPGA, Mike Lewis
    • Re: Tristate bus on spartan FPGA, aravind
• Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL, fastgreen2000
  • Re: Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL, Laurent Pinchart
  • Re: Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL, Martin Thompson
    • Re: Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL, Gabor
      • Re: Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL, Gabor
      • Re: Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL, fastgreen2000
      • Re: Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL, fastgreen2000
      • Re: Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL, Andy Peters
      • Re: Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL, Martin Thompson
• Virtex-4 SELECT MAP configuration, Pasacco
  • Re: Virtex-4 SELECT MAP configuration, jerzy.gbur@xxxxxxxxx
• Directing data to DDR, S
• Altera / Lattice / Xilinx CPLDs ?, Amontec, Larry
  • Re: Altera / Lattice / Xilinx CPLDs ?, austin
  • Re: Altera / Lattice / Xilinx CPLDs ?, John_H
    • Re: Altera / Lattice / Xilinx CPLDs ?, Uwe Bonnes
      • Re: Altera / Lattice / Xilinx CPLDs ?, John_H
      • Re: Altera / Lattice / Xilinx CPLDs ?, Uwe Bonnes
    • Re: Altera / Lattice / Xilinx CPLDs ?, Jim Granville
    • Re: Altera / Lattice / Xilinx CPLDs ?, Jon Elson
  • Re: Altera / Lattice / Xilinx CPLDs ?, ghelbig
    • Re: Altera / Lattice / Xilinx CPLDs ?, Gabor
  • Re: Altera / Lattice / Xilinx CPLDs ?, vasile
  • Re: Altera / Lattice / Xilinx CPLDs ?, Jim Granville
• ECP2/M und Serdes, Martin Sauer
• global clock on virtex5 question, vasile
  • Re: global clock on virtex5 question, Ed McGettigan
    • Re: global clock on virtex5 question, vasile
      • Re: global clock on virtex5 question, Ed McGettigan
      • Re: global clock on virtex5 question, vasile
• Unexplained behavior with DDR2 controller on Xilinx V5, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
  • Re: Unexplained behavior with DDR2 controller on Xilinx V5, Brad Smallridge
    • Re: Unexplained behavior with DDR2 controller on Xilinx V5, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
      • Re: Unexplained behavior with DDR2 controller on Xilinx V5, jacobusn@xxxxxxxxxx
      • Re: Unexplained behavior with DDR2 controller on Xilinx V5, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
• ASAP 2008: Preliminary Call for Papers, j4murali@xxxxxxxxx
• Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or..., Andrew FPGA
  • <Possible follow-ups>
  • Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or..., Tobias Weingartner
  • Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or..., Jim Granville
    • Message not available
      • Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or..., Jeff Cunningham
• [ANNOUNCE] YARDstick - custom processor development toolset, Uncle Noah
  • Re: YARDstick - custom processor development toolset, Uncle Noah
    • Re: YARDstick - custom processor development toolset, Uncle Noah
• FPGA power optimize! Help, embeddedexpert2007
• sounds, carlmorada
  • Re: sounds, Icky Thwacket
    • Re: sounds, MikeJ
• XAPP806 issues DCM Phase Shift, Brad Smallridge
• Virtex II pro design question, Manny
  • Re: Virtex II pro design question, Daniel S.
    • Re: Virtex II pro design question, Manny
• Beginner Advice (Languages, tools etc.), RL
  • Re: Beginner Advice (Languages, tools etc.), Mike Treseler
  • Re: Beginner Advice (Languages, tools etc.), Jeff Cunningham
    • Re: Beginner Advice (Languages, tools etc.), Nico Coesel
      • Re: Beginner Advice (Languages, tools etc.), Jeff Cunningham
  • Re: Beginner Advice (Languages, tools etc.), HT-Lab
  • Re: Beginner Advice (Languages, tools etc.), James Harris
  • Re: Beginner Advice (Languages, tools etc.), Bob Perlman
    • Re: Beginner Advice (Languages, tools etc.), RL
      • Re: Beginner Advice (Languages, tools etc.), Andrew FPGA
      • Re: Beginner Advice (Languages, tools etc.), Jeff Cunningham
      • Re: Beginner Advice (Languages, tools etc.), HT-Lab
      • Re: Beginner Advice (Languages, tools etc.), Bob Perlman
  • Re: Beginner Advice (Languages, tools etc.), Jim Granville
• Learn About High-speed Serial Connectivity & FPGAs - for FREE, Navneet Rao
• add_file -verilog +define ..... filename.v, Abhi
• post translate and post PAR problems with XST and Modelsim, alleynb
  • Re: post translate and post PAR problems with XST and Modelsim, Gabor
• Spartan-3E Slave Serial Configuration, Andrew Greensted
  • Re: Spartan-3E Slave Serial Configuration, Symon
    • Re: Spartan-3E Slave Serial Configuration, Andrew Greensted
      • Re: Spartan-3E Slave Serial Configuration, John Larkin
  • Re: Spartan-3E Slave Serial Configuration, Brian Davis
    • Re: Spartan-3E Slave Serial Configuration, Andy
• Physical Design Contribution to FPGA/CPLD success, acd
  • Re: Physical Design Contribution to FPGA/CPLD success, Mike Treseler
    • Re: Physical Design Contribution to FPGA/CPLD success, Peter Alfke
    • Re: Physical Design Contribution to FPGA/CPLD success, acd
      • Re: Physical Design Contribution to FPGA/CPLD success, Mike Treseler
      • Re: Physical Design Contribution to FPGA/CPLD success, Mike Treseler
  • Re: Physical Design Contribution to FPGA/CPLD success, Andy
    • Re: Physical Design Contribution to FPGA/CPLD success, glen herrmannsfeldt
  • Re: Physical Design Contribution to FPGA/CPLD success, Jim Granville
    • Re: Physical Design Contribution to FPGA/CPLD success, glen herrmannsfeldt
• Xilinx GSRD reference design and 3rd party synthesizer, llandre
• Is post-place and route simulation useful?, GaLaKtIkUs™
  • Re: Is post-place and route simulation useful?, KJ
    • Re: Is post-place and route simulation useful?, GaLaKtIkUs?
  • Re: Is post-place and route simulation useful?, Kim Enkovaara
    • Re: Is post-place and route simulation useful?, Andy
      • Re: Is post-place and route simulation useful?, HT-Lab
  • Re: Is post-place and route simulation useful?, Mike Treseler
• Open-Source VHDL Synthesis for FPSLIC?, LowSNR
  • Re: Open-Source VHDL Synthesis for FPSLIC?, Mike Treseler
  • Re: Open-Source VHDL Synthesis for FPSLIC?, Eric Smith
• Virtex-4 PCB design, cstring625
  • Re: Virtex-4 PCB design, Gabor
• MicroBlaze Tutorial, Brad Smallridge
  • Re: MicroBlaze Tutorial, John Williams
    • Re: MicroBlaze Tutorial, Brad Smallridge
      • Re: MicroBlaze Tutorial, svenand
• Problem with Microblaze max clocking, Andrea05
  • Re: Problem with Microblaze max clocking, John_H
  • Re: Problem with Microblaze max clocking, Göran Bilski
• genmcs.pl for a V4FX60 aka loading the cache from the prom on a multi processor device, dcaulfield
• Virtex5 PLL for DDR2 interface, Barry
  • Re: Virtex5 PLL for DDR2 interface, austin
• Peripheral Trouble!, MJ Pearson
  • Re: Peripheral Trouble!, Andrea05
    • Re: Peripheral Trouble!, MJ Pearson
      • Re: Peripheral Trouble!, John McCaskill
• Xilinx System Generator Error!, james . lbs
• overloading ' operators in VHDL, Dolphin
  • Re: overloading ' operators in VHDL, Mark McDougall
  • Re: overloading ' operators in VHDL, RCIngham
• Opening for Senior Level Design Test Engineer, Ram
• Urgent requirement for Sr.Engineer (Verification), Ram
• Excellent Opening For ASIC Design Engineer !!!!!, Ram
• Xilinx ISP JTAG progaramming (XCF32P using GPIO from V4FX12), cpope
  • Re: Xilinx ISP JTAG progaramming (XCF32P using GPIO from V4FX12), Alan Nishioka
    • Re: Xilinx ISP JTAG progaramming (XCF32P using GPIO from V4FX12), cpope
      • Re: Xilinx ISP JTAG progaramming (XCF32P using GPIO from V4FX12), Alan Nishioka
  • Re: Xilinx ISP JTAG progaramming (XCF32P using GPIO from V4FX12), Petter Gustad
    • Re: Xilinx ISP JTAG progaramming (XCF32P using GPIO from V4FX12), cpope
      • Re: Xilinx ISP JTAG progaramming (XCF32P using GPIO from V4FX12), neilla
      • Re: Xilinx ISP JTAG progaramming (XCF32P using GPIO from V4FX12), cpope
      • Re: Xilinx ISP JTAG progaramming (XCF32P using GPIO from V4FX12), Petter Gustad
• project in chennai, Kanjithatha
• XAPP851 fifo36 missing, Brad Smallridge
  • Re: XAPP851 fifo36 missing, Brad Smallridge
    • Re: XAPP851 fifo36 missing, Kevin Neilson
      • Re: XAPP851 fifo36 missing, Brad Smallridge
• Ethernet Code Problem with Xilinx Spartan3E, calkins
  • Re: Ethernet Code Problem with Xilinx Spartan3E, vitek . vitek
• Altera + ARM Cortex-M1, vitek . vitek
• VHDL Design Pattern Book, Erik Anderson
  • Re: VHDL Design Pattern Book, Steven Derrien
• precision errors. microblaze vs matlab single precision... huh?, chriskoh
• Command line quartus_pgm very slow, Steven Derrien
  • Re: Command line quartus_pgm very slow, Petter Gustad
• [Nios II] How fast the cpu in Nios II can reach in the Cycone ?, lexluthor
  • Re: [Nios II] How fast the cpu in Nios II can reach in the Cycone ?, Górski Adam
  • Re: [Nios II] How fast the cpu in Nios II can reach in the Cycone ?, Iwo Mergler
  • Re: [Nios II] How fast the cpu in Nios II can reach in the Cycone ?, Ben Jackson
• ML410 Board & 1GB DDR2 DIMM Problem, Wren
  • Re: ML410 Board & 1GB DDR2 DIMM Problem, Brad Smallridge
    • Re: ML410 Board & 1GB DDR2 DIMM Problem, Wren
      • Re: ML410 Board & 1GB DDR2 DIMM Problem, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
• Address sensitive process, Xilinx virtex2pro, yoni . lan
  • Re: Address sensitive process, Xilinx virtex2pro, Brad Smallridge
    • Re: Address sensitive process, Xilinx virtex2pro, Symon
      • Re: Address sensitive process, Xilinx virtex2pro, Brad Smallridge
      • Re: Address sensitive process, Xilinx virtex2pro, Andy
      • Re: Address sensitive process, Xilinx virtex2pro, Brad Smallridge
      • Re: Address sensitive process, Xilinx virtex2pro, Andy
      • Re: Address sensitive process, Xilinx virtex2pro, Symon
  • Re: Address sensitive process, Xilinx virtex2pro, Erik Anderson
  • Re: Address sensitive process, Xilinx virtex2pro, Jeff Cunningham
• FPGA Archives, Brad Smallridge
  • Re: FPGA Archives, Martin Thompson
    • Re: FPGA Archives, Brad Smallridge
      • Re: FPGA Archives, MM
      • Re: FPGA Archives, Martin Thompson
  • Re: FPGA Archives, Philip Freidin
• Good VHDL reference?, Nico Coesel
  • Re: Good VHDL reference?, Symon
  • Re: Good VHDL reference?, Eli Bendersky
    • Re: Good VHDL reference?, xenix
    • Re: Good VHDL reference?, Dan K
      • Re: Good VHDL reference?, Weng Tianxiang
      • Re: Good VHDL reference?, Andy
• Stratix III Memory usage efficiency, davew
  • Re: Stratix III Memory usage efficiency, Mike Treseler
    • Re: Stratix III Memory usage efficiency, davew
      • Re: Stratix III Memory usage efficiency, Kim Enkovaara
      • Re: Stratix III Memory usage efficiency, Mike Treseler
  • Re: Stratix III Memory usage efficiency, Subroto Datta
    • Re: Stratix III Memory usage efficiency, davew
• application about hardeware attributes, J.Wild
• microblaze toolchain compilation question, taco
  • Re: microblaze toolchain compilation question, John Williams
    • Re: microblaze toolchain compilation question, taco
      • Re: microblaze toolchain compilation question, Vasanth Asokan
• Re: Fighting with Compact Flash, kron
• Re: Uses of Gray code in digital design, John_H
• hydraxc, u_stadler@xxxxxxxx
• Xilinx core generator MIG module generates a slow timing for a DDR2 SDRAM controller, damicha
  • Re: Xilinx core generator MIG module generates a slow timing for a DDR2 SDRAM controller, Göran Bilski
    • Re: Xilinx core generator MIG module generates a slow timing for a DDR2 SDRAM controller, damicha
      • Re: Xilinx core generator MIG module generates a slow timing for a DDR2 SDRAM controller, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
      • Re: Xilinx core generator MIG module generates a slow timing for a DDR2 SDRAM controller, damicha
• Question about Virtex-4 DCM, ghelbig
  • Re: Question about Virtex-4 DCM, austin
    • Re: Question about Virtex-4 DCM, ghelbig
• 1/2 Convolutional Encoding of CNAV Data, mits130
• VHDL Synthesis Error, ray . delvecchio
  • Re: VHDL Synthesis Error, Mike Treseler
    • Re: VHDL Synthesis Error, Andy
      • Re: VHDL Synthesis Error, Ray D.
      • Re: VHDL Synthesis Error, Brad Smallridge
• LVDS pin placing on CYCLON II problem, Górski Adam
  • Re: LVDS pin placing on CYCLON II problem, Rob
    • Re: LVDS pin placing on CYCLON II problem, Górski Adam
      • Re: LVDS pin placing on CYCLON II problem, Górski Adam
• Quick question for an Altera wizard, nospam
  • Re: Quick question for an Altera wizard, Daniel S.
    • Re: Quick question for an Altera wizard, Ben Jackson
      • Re: Quick question for an Altera wizard, KJ
      • Re: Quick question for an Altera wizard, KJ
• Minimize power consumption, drop669
  • Re: Minimize power consumption, John_H
    • Re: Minimize power consumption, drop669
      • Re: Minimize power consumption, Jim Granville
      • Re: Minimize power consumption, drop669
      • Re: Minimize power consumption, Jim Granville
      • Re: Minimize power consumption, John_H
      • Re: Minimize power consumption, drop669
    • Re: Minimize power consumption, John_H
  • Re: Minimize power consumption, glen herrmannsfeldt
    • Re: Minimize power consumption, drop669
      • Re: Minimize power consumption, John_H
• Anyway to stop Altera Stratix II SignalTap data acquisition, frankzhangee
  • Re: Anyway to stop Altera Stratix II SignalTap data acquisition, Mark McDougall
• Help getting sdram running with EDK., johnblake2000@xxxxxxxxx
  • Re: Help getting sdram running with EDK., John Williams
    • Re: Help getting sdram running with EDK., johnblake2000@xxxxxxxxx
  • Re: Help getting sdram running with EDK., Alan Nishioka
    • Re: Help getting sdram running with EDK., johnblake2000@xxxxxxxxx
• Nios II -- Why does this error occur ?, lexluthor
  • Re: Nios II -- Why does this error occur ?, newsleecher@xxxxxxxx
• RE: FPGA/VHDL digital Design permanent role - Oxford, khomeyard
• SRAM on Cyclone Devices, devices
  • Re: SRAM on Cyclone Devices, devices
• How to simple convert a hex or mif file from Altera to Xilinx coe file?, Bernard Esteban
  • Re: How to simple convert a hex or mif file from Altera to Xilinx coe file?, Gabor
    • Re: How to simple convert a hex or mif file from Altera to Xilinx coe file?, Mark McDougall
• Re: Xilinx FPGA Based Board Problem, Piyush Kaul
• [Nios II] How does the PIO Core generate a interrupt?, lexluthor
  • Re: How does the PIO Core generate a interrupt?, mjl296@xxxxxxxxxxx
    • Re: How does the PIO Core generate a interrupt?, lexluthor
  • Re: [Nios II] How does the PIO Core generate a interrupt?, bigboss25@xxxxxxxxxxx
• Rocket IO clock, vasile
  • Re: Rocket IO clock, Ed McGettigan
• DDR Simulation via MIG, motty
  • Re: DDR Simulation via MIG, motty
    • Re: DDR Simulation via MIG, Duth
• VCCAUX too high on a Spartan 3 design, Dan K
  • Re: VCCAUX too high on a Spartan 3 design, Andrew Holme
    • Re: VCCAUX too high on a Spartan 3 design, Peter Alfke
      • Re: VCCAUX too high on a Spartan 3 design, Jim Granville
      • Re: VCCAUX too high on a Spartan 3 design, Peter Alfke
      • Re: VCCAUX too high on a Spartan 3 design, vasile
      • Re: VCCAUX too high on a Spartan 3 design, jonpry
  • Re: VCCAUX too high on a Spartan 3 design, John Larkin
    • Re: VCCAUX too high on a Spartan 3 design, Peter Alfke
      • Re: VCCAUX too high on a Spartan 3 design, vasile
      • Re: VCCAUX too high on a Spartan 3 design, Dan K
• ANNC: New Boundary-Scan Software, skswrus
  • Re: ANNC: New Boundary-Scan Software, Uwe Bonnes
  • Re: ANNC: New Boundary-Scan Software, Uwe Bonnes
  • Message not available
    • Re: ANNC: New Boundary-Scan Software, skswrus
      • Re: ANNC: New Boundary-Scan Software, comp.arch.fpga
• Problem locking a DCM driven by FX output of another DCM, MM
  • Re: Problem locking a DCM driven by FX output of another DCM, MM
    • Re: Problem locking a DCM driven by FX output of another DCM, John McCaskill
      • Re: Problem locking a DCM driven by FX output of another DCM, MM
      • Re: Problem locking a DCM driven by FX output of another DCM, John McCaskill
      • Re: Problem locking a DCM driven by FX output of another DCM, MM
      • Re: Problem locking a DCM driven by FX output of another DCM, John McCaskill
      • Re: Problem locking a DCM driven by FX output of another DCM, MM
      • Re: Problem locking a DCM driven by FX output of another DCM, John McCaskill
      • Re: Problem locking a DCM driven by FX output of another DCM, John_H
      • Re: Problem locking a DCM driven by FX output of another DCM, MM
      • Re: Problem locking a DCM driven by FX output of another DCM, John_H
      • Re: Problem locking a DCM driven by FX output of another DCM, MM
      • Re: Problem locking a DCM driven by FX output of another DCM, Symon
      • Re: Problem locking a DCM driven by FX output of another DCM, MM
      • Re: Problem locking a DCM driven by FX output of another DCM, John McCaskill
      • Re: Problem locking a DCM driven by FX output of another DCM, MM
• Clock boundary crossing, axr0284
  • Re: Clock boundary crossing, Peter Alfke
  • Re: Clock boundary crossing, kkoorndyk
    • Re: Clock boundary crossing, Hal Murray
    • Re: Clock boundary crossing, Douglas
      • Re: Clock boundary crossing, Hal Murray
      • Re: Clock boundary crossing, Mike Treseler
      • Re: Clock boundary crossing, Hal Murray
      • Re: Clock boundary crossing, Alan Nishioka
      • Re: Clock boundary crossing, glen herrmannsfeldt
• Free downloadable PDF graph paper., Symon
  • Re: Free downloadable PDF graph paper., Gabor
  • Re: Free downloadable PDF graph paper., Kevin Neilson
    • Re: Free downloadable PDF graph paper., Martin Thompson
    • Re: Free downloadable PDF graph paper., Guenter
• Is it possible to perform gate level simulation on a design without a reset?, aclegg1986
  • Re: Is it possible to perform gate level simulation on a design without a reset?, Peter Alfke
  • Re: Is it possible to perform gate level simulation on a design without a reset?, John_H
    • Re: Is it possible to perform gate level simulation on a design without a reset?, KJ
      • Re: Is it possible to perform gate level simulation on a design without a reset?, John_H
      • Re: Is it possible to perform gate level simulation on a design without a reset?, KJ
      • Re: Is it possible to perform gate level simulation on a design without a reset?, aclegg1986
      • Re: Is it possible to perform gate level simulation on a design without a reset?, John_H
      • Re: Is it possible to perform gate level simulation on a design without a reset?, aclegg1986
      • Re: Is it possible to perform gate level simulation on a design without a reset?, Andy
      • Re: Is it possible to perform gate level simulation on a design without a reset?, John_H
      • Re: Is it possible to perform gate level simulation on a design without a reset?, Ray Andraka
• load/read/ commands assembly PowerPC. Help Needed!, xenix
  • Re: load/read/ commands assembly PowerPC. Help Needed!, John McCaskill
    • Re: load/read/ commands assembly PowerPC. Help Needed!, xenix
      • Re: load/read/ commands assembly PowerPC. Help Needed!, xenix
      • Re: load/read/ commands assembly PowerPC. Help Needed!, John McCaskill
  • Re: load/read/ commands assembly PowerPC. Help Needed!, Peter Ryser
    • Re: load/read/ commands assembly PowerPC. Help Needed!, xenix
    • Re: load/read/ commands assembly PowerPC. Help Needed!, xenix
      • Re: load/read/ commands assembly PowerPC. Help Needed!, xenix
• Question about timing of Xilinx Core generated counter, fl
• JTAG CPLD Configuration, Keith
• REGARDING ILA in FPGA EDITOR, bunty
• FATAL ERROR ISE9.1i, james . lbs
  • Re: FATAL ERROR ISE9.1i, Helmut
    • Re: FATAL ERROR ISE9.1i, andrea . pellegrini
• 【Nios II】How Can I Find Out These Functions ？, hezhikuan2007
  • Re: ¡¾Nios II¡¿How Can I Find Out These Functions £¿, Mark McDougall
  • Re: ?Nios II?How Can I Find Out These Functions ?, Iwo Mergler
    • Re: ?Nios II?How Can I Find Out These Functions ?, lexluthor
• Re: BlockRAM connection error, Paulo Dutra
  • Re: BlockRAM connection error, young
• How to deal with the tempary coefficient in the FPGA design, ZHI
  • Re: How to deal with the tempary coefficient in the FPGA design, glen herrmannsfeldt
    • Re: How to deal with the tempary coefficient in the FPGA design, ZHI
      • Re: How to deal with the tempary coefficient in the FPGA design, glen herrmannsfeldt
    • Re: How to deal with the tempary coefficient in the FPGA design, ZHI
    • Re: How to deal with the tempary coefficient in the FPGA design, ZHI
• clock skew problems, michel . talon
  • Re: clock skew problems, Gabor
  • Re: clock skew problems, Joseph Samson
    • Re: clock skew problems, michel . talon
      • Re: clock skew problems, Gabor
• EDK9.1 linux registration fails (vista ok), rponsard
  • Re: EDK9.1 linux registration fails (vista ok), MM
• Re: DDR controller - best device to perform, pgw
• warning 1780 shown while synthesis, in xilinx 6.3i, ankur
• vnavigator problem, kkoorndyk
• Multiple CPLDs on a PCB., NickNitro
  • Re: Multiple CPLDs on a PCB., Jim Granville
    • Re: Multiple CPLDs on a PCB., NickNitro
      • Re: Multiple CPLDs on a PCB., Jim Granville
      • Re: Multiple CPLDs on a PCB., Hal Murray
      • Re: Multiple CPLDs on a PCB., Jon Elson
    • Re: Multiple CPLDs on a PCB., Mike Harrison
  • Re: Multiple CPLDs on a PCB., Gabor
    • Re: Multiple CPLDs on a PCB., NickNitro
      • Re: Multiple CPLDs on a PCB., Peter Alfke
      • Re: Multiple CPLDs on a PCB., NickNitro
      • Re: Multiple CPLDs on a PCB., Peter Alfke
      • Re: Multiple CPLDs on a PCB., NickNitro
  • Re: Multiple CPLDs on a PCB., John Larkin
  • Re: Multiple CPLDs on a PCB., Zara
• Actel Designer - Specifying multicycle path constraints (via .sdc file) when using synchronous clock enables, David
  • Re: Actel Designer - Specifying multicycle path constraints (via .sdc file) when using synchronous clock enables, HT-Lab
• Import Xilinx SDK Project in Wind River Workbench, LilacSkin
• ERROR:NgdBuild:604 with user ipcore, L. Schreiber
  • <Possible follow-ups>
  • ERROR:NgdBuild:604 with user ipcore, L. Schreiber
    • Re: ERROR:NgdBuild:604 with user ipcore, Gabor
      • Re: ERROR:NgdBuild:604 with user ipcore, L. Schreiber
      • Re: ERROR:NgdBuild:604 with user ipcore, Paulo Dutra
      • Re: ERROR:NgdBuild:604 with user ipcore, L. Schreiber
• Actel IGLOO FPGA has lower power consumption then Xilinx Coolrunner-II CPLD?, ikogan
  • Re: Actel IGLOO FPGA has lower power consumption then Xilinx Coolrunner-II CPLD?, Douglas
• Help on OCM BRAM intercafe and assembly code, xenix
• Help on ocm, xenix
• Re: Spartan 3E - Readback via JTAG, Uwe Bonnes
• Re: VHDL core to read/write to Bram_Block., Pablo
• GTKWave 3.1.0 for win32, mk
• [Nios II] How Can I define the pio inputs as a interrupt?, hezhikuan2007
  • Re: [Nios II] How Can I define the pio inputs as a interrupt?, Mark McDougall
    • Re: How Can I define the pio inputs as a interrupt?, hezhikuan2007
• Low-level FPGA programming?, drop669
  • Re: Low-level FPGA programming?, Paul Leventis
  • Re: Low-level FPGA programming?, drop669
    • Re: Low-level FPGA programming?, Andreas Ehliar
      • Re: Low-level FPGA programming?, austin
      • Re: Low-level FPGA programming?, Jon Beniston
      • Re: Low-level FPGA programming?, Andreas Ehliar
      • Re: Low-level FPGA programming?, cs_posting
  • Re: Low-level FPGA programming?, RedskullDC
• Cannot pass par in tcl, Xilinx webpack 9.1., fl
• Beginning FPGA programming, James Harris
  • FPGA CPU, James Harris
    • Re: FPGA CPU, Andreas Ehliar
      • Re: FPGA CPU, James Harris
      • Re: FPGA CPU, Andreas Ehliar
      • Re: FPGA CPU, Andreas Ehliar
      • Re: FPGA CPU, glen herrmannsfeldt
      • Re: FPGA CPU, Göran Bilski
      • Re: FPGA CPU, glen herrmannsfeldt
      • Re: FPGA CPU, James Harris
      • Re: FPGA CPU, Frank Buss
      • Re: FPGA CPU, glen herrmannsfeldt
      • Re: FPGA CPU, fpga_toys
      • Re: FPGA CPU, James Harris
      • Re: FPGA CPU, fpga_toys
      • Re: FPGA CPU, James Harris
    • Re: FPGA CPU, fpga_toys
      • Re: FPGA CPU, James Harris
      • Re: FPGA CPU, fpga_toys
      • Re: FPGA CPU, fpga_toys
  • Re: Beginning FPGA programming, glen herrmannsfeldt
• opb_timer interrupt self test problem, dormanpeter1
  • Re: opb_timer interrupt self test problem, benradu
    • Re: opb_timer interrupt self test problem, DoPeti
• V5 Configuration via SPI, Sean Durkin
  • Re: V5 Configuration via SPI, austin
    • Re: V5 Configuration via SPI, Sean Durkin
      • Re: V5 Configuration via SPI, austin
      • Re: V5 Configuration via SPI, Sean Durkin
      • Re: V5 Configuration via SPI, Max Baker
  • Re: V5 Configuration via SPI, John Larkin
• Re: PCIe question, John Adair
• Re: Spartan 3E starter kit (Rev.D) modification : 3E500 -> 3E1200, John Adair
• Re: Spartan3E and DDR termination, Guru
  • Re: Spartan3E and DDR termination, Ben Jackson
  • <Possible follow-ups>
  • Re: Spartan3E and DDR termination, vasile
    • Re: Spartan3E and DDR termination, Gabor
      • Re: Spartan3E and DDR termination, vasile
• flip-flop enable, al . basili
  • Re: flip-flop enable, Ralf Hildebrandt
• Re: Strange behaviour of a design, Kunal
  • <Possible follow-ups>
  • Re: Strange behaviour of a design, Kunal
    • Re: Strange behaviour of a design, markus . jank
• Re: Chip Designing made Easy, Antti
• Re: Memory bandwidth of the 3A kit, Antti
• Re: Partial reconfiguration using ICAP, Sean Durkin
• Re: comparison with embedded processor, Daniel S.
• Interesting FPGA/JTAG project., Symon
• Re: PCB Layers, Symon
  • Re: PCB Layers, maxascent
    • Re: PCB Layers, Symon
  • Re: PCB Layers, KJ
    • Re: PCB Layers, Symon
• Re: Is it possible to make bit files generated by Xilinx ISE readable?, glen herrmannsfeldt
• Re: Newbie with ISE 9_2_02i_lin gets error : Process "Translate" failed, Bob Smith
• Re: Xilinx ML40x Mouse VHDL Wanted, ghelbig
• Re: PCB Impedance Control, PeteS
  • <Possible follow-ups>
  • Re: PCB Impedance Control, John Larkin
    • Re: PCB Impedance Control, Symon
      • Re: PCB Impedance Control, Hal Murray
      • Re: PCB Impedance Control, John Larkin
      • Re: PCB Impedance Control, Symon
      • Re: PCB Impedance Control, John Larkin
      • Re: PCB Impedance Control, glen herrmannsfeldt
      • Re: PCB Impedance Control, John Larkin
      • Re: PCB Impedance Control, Andrew Burnside
      • Re: PCB Impedance Control, glen herrmannsfeldt
      • Re: PCB Impedance Control, vasile
      • Re: PCB Impedance Control, John Larkin
      • Re: PCB Impedance Control, glen herrmannsfeldt
      • Re: PCB Impedance Control, Hal Murray
      • Re: PCB Impedance Control, glen herrmannsfeldt
      • Re: PCB Impedance Control, John Larkin
      • Re: PCB Impedance Control, glen herrmannsfeldt
      • Re: PCB Impedance Control, PeteS
      • Re: PCB Impedance Control, John Larkin
      • Re: PCB Impedance Control, PeteS
      • Re: PCB Impedance Control, John_H
      • Re: PCB Impedance Control, Symon
    • Re: PCB Impedance Control, Hal Murray
      • Re: PCB Impedance Control, John Larkin
    • Re: PCB Impedance Control, vasile
      • Re: PCB Impedance Control, John Larkin
      • Re: PCB Impedance Control, Symon
      • Re: PCB Impedance Control, John Larkin
      • Re: PCB Impedance Control, Symon
      • Re: PCB Impedance Control, John Larkin
      • Re: PCB Impedance Control, glen herrmannsfeldt
      • Re: PCB Impedance Control, glen herrmannsfeldt
      • Re: PCB Impedance Control, Symon
      • Re: PCB Impedance Control, John_H
      • Re: PCB Impedance Control, Symon
      • Re: PCB Impedance Control, glen herrmannsfeldt
      • Re: PCB Impedance Control, John Larkin
      • Re: PCB Impedance Control, glen herrmannsfeldt
      • Re: PCB Impedance Control, PeteS
      • Re: PCB Impedance Control, John_H
      • Re: PCB Impedance Control, glen herrmannsfeldt
  • Re: PCB Impedance Control, kayrock66
    • Re: PCB Impedance Control, John Larkin
• Re: PLL Power and m/n ratio, fpgabuilder
• Re: An FPGA startup is seeking testcase from potential customers, fpgabuilder
  • <Possible follow-ups>
  • Re: An FPGA startup is seeking testcase from potential customers, j . d . morrison
• How to add additional FSL interface to customized IP?, David Chen
  • Re: How to add additional FSL interface to customized IP?, Göran Bilski
• Re: Die size, pitch size?, Pasacco
  • Re: Die size, pitch size?, Peter Alfke
  • Re: Die size, pitch size?, John_H
  • <Possible follow-ups>
  • Re: Die size, pitch size?, Jim Granville
  • Re: Die size, pitch size?, j . d . morrison
    • Re: Die size, pitch size?, Pasacco

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