Re: Output signals not synchronized

"EEngineer" <maricic@xxxxxxxxx> wrote in message
news:1188426999.764557.233750@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
there are also UCF lines:

NET ctrl_data<*> SLEW = FAST;
NET ctrl_data<*> DRIVE = 2;
NET ctrl_data<*> IOSTANDARD = LVCMOS33;

To start with, your timing constraint of OFFSET = OUT 100 ps AFTER is not
something that will make your outputs happen coincident with your clock,
it's a specification that will simply fail in the place & route and timing
analyzer. Take a look. The fastest your outputs will go depend on how fast
an IOB register can deliver its output relative to your global clock. These
numbers are documented and easy to prototype.

Second, the 2 mA drive level will give you a slower rise/fall. The skew in
your output signal time can - depending on your load - be a noticeable time
difference.

Third, the logic analyzer is an asynchronous device which will usually
provide a 2.5 ns uncertainty in your results leaving only a 2.5 ns
difference not explained by the test equipment.

Please find the online documentation (or a Xilinx class) that describes what
you can and cannot do with constraints. This fundamental information
usually is only understood after an engineer can't understand why their
design isn't working. Learn it.


.

Relevant Pages

  • Re: Signal Set-up Before CLK Rise
    ... If "clock" is delivered by your VHDL device, ... Gate Net ... Cell:in->out fanout Delay Delay Logical Name ... Timing constraint: Default OFFSET IN BEFORE for Clock 'S_THIS_4' ...
    (comp.lang.vhdl)
  • Re: Output signals not synchronized
    ... your timing constraint of OFFSET = OUT 100 ps AFTER is not ... an IOB register can deliver its output relative to your global clock. ... If you need your outputs to have very low skew, ... your outputs are generated by fabric flip-flops it is very hard ...
    (comp.arch.fpga)
  • Re: question: timing constraint for clock enable
    ... > Let's assume I have a global clock running at 80 MHz and a 2 bit counter ... > running from this clock, which generates a 20 MHz clock enable signal. ... > Is there a way to apply any sort of timing constraint to the clock enable ... > Stephan Flock ...
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  • question: timing constraint for clock enable
    ... Let's assume I have a global clock running at 80 MHz and a 2 bit counter ... Is there a way to apply any sort of timing constraint to the clock enable ... Stephan Flock ...
    (comp.arch.fpga)