comp.arch.fpga

Date Index

Chip Designing made Easy, robin
- Re: Chip Designing made Easy, John_H
BlockRAM connection error, young
what does asynchronous loop mean?, asic1234@xxxxxxxxx
- Re: what does asynchronous loop mean?, Hal Murray
Xilinx ML40x Mouse VHDL Wanted, Brad Smallridge
signal termination in spartan 3e starter kit, asimatta@xxxxxxxxxxx
Simple Project involving microblaze, Amir
- Re: Simple Project involving microblaze, young
Memory bandwidth of the 3A kit, Simon
- Re: Memory bandwidth of the 3A kit, Simon
Wifi with a Virtex 4, Peter Mendham
Is it possible to make bit files generated by Xilinx ISE readable?, Wei Wang
- Re: Is it possible to make bit files generated by Xilinx ISE readable?, John_H
  - Re: Is it possible to make bit files generated by Xilinx ISE readable?, Jim Wu
- Re: Is it possible to make bit files generated by Xilinx ISE readable?, MM
Xilinx blockram FIFO async reset annoys me (and Modelsim), Frai
Spartan 3E - Readback via JTAG, Benni V.
- Re: Spartan 3E - Readback via JTAG, Uwe Bonnes
  - Re: Spartan 3E - Readback via JTAG, Benni V.
An FPGA startup is seeking testcase from potential customers, siliconbluetechnology
- Re: An FPGA startup is seeking testcase from potential customers, Jim Granville
  - Re: An FPGA startup is seeking testcase from potential customers, siliconbluetechnology
Die size, pitch size?, Pasacco
- Re: Die size, pitch size?, Uwe Bonnes
  - Re: Die size, pitch size?, Pasacco
    - Re: Die size, pitch size?, Peter Alfke
    - Re: Die size, pitch size?, Pasacco
    - Re: Die size, pitch size?, Symon
    - Re: Die size, pitch size?, Pasacco
    - Re: Die size, pitch size?, Peter Alfke
Reconfiguration of a XUP Board, Sebastian Goller
- Re: Reconfiguration of a XUP Board, Gabor
PCB Impedance Control, maxascent
- Re: PCB Impedance Control, Symon
  - Re: PCB Impedance Control, PeteS
    - Re: PCB Impedance Control, John_H
    - Re: PCB Impedance Control, Symon
    - Re: PCB Impedance Control, Brian Drummond
    - Re: PCB Impedance Control, Bob Perlman
    - Re: PCB Impedance Control, John_H
    - Re: PCB Impedance Control, PeteS
    - Re: PCB Impedance Control, John_H
    - Re: PCB Impedance Control, PeteS
    - Re: PCB Impedance Control, PeteS
Spartan 3E starter kit (Rev.D) modification : 3E500 -> 3E1200, dormanpeter1
- Re: Spartan 3E starter kit (Rev.D) modification : 3E500 -> 3E1200, emu
  - Re: Spartan 3E starter kit (Rev.D) modification : 3E500 -> 3E1200, dormanpeter1
modelsim, fazulu deen
- Re: modelsim, Jon Beniston
  - Re: modelsim, fazulu deen
    - Re: modelsim, fpgabuilder
    - Re: modelsim, fazulu deen
    - Re: modelsim, fpgabuilder
Spartan3E and DDR termination, Guru
- Re: Spartan3E and DDR termination, Gabor
  - Re: Spartan3E and DDR termination, Gabor
- Re: Spartan3E and DDR termination, Bob
- Re: Spartan3E and DDR termination, Brian Drummond
Xilinx FPGA Based Board Problem, Piyush Kaul
- Re: Xilinx FPGA Based Board Problem, Martin Thompson
- Re: Xilinx FPGA Based Board Problem, SKatsyuba
Where is Command Reg and Status Reg as mentioned in PCI system architecture (Mindshare) in generated pci32 core?, Ace
- Re: Where is Command Reg and Status Reg as mentioned in PCI system architecture (Mindshare) in generated pci32 core?, Brian Drummond
  - Re: Where is Command Reg and Status Reg as mentioned in PCI system architecture (Mindshare) in generated pci32 core?, Ace
    - Re: Where is Command Reg and Status Reg as mentioned in PCI system architecture (Mindshare) in generated pci32 core?, Brian Drummond
SDF File basics, asic1234@xxxxxxxxx
- Re: SDF File basics, Jon Beniston
  - Re: SDF File basics, asic1234@xxxxxxxxx
Output signals not synchronized, EEngineer
- Re: Output signals not synchronized, EEngineer
  - Re: Output signals not synchronized, John_H
    - Re: Output signals not synchronized, Gabor
    - Re: Output signals not synchronized, s . stanislava
    - Re: Output signals not synchronized, EEngineer
    - Re: Output signals not synchronized, Gabor
    - Re: Output signals not synchronized, EEngineer
    - Re: Output signals not synchronized, Andy Peters
    - Re: Output signals not synchronized, EEngineer
Difference in the JTAG instructions between Virtex and Virtex II, shadabambat1@xxxxxxxxx
Registered output for Altera on-chip memory, Edmond Coté
- Re: Registered output for Altera on-chip memory, fpgabuilder
PCIe question, vsurducan@xxxxxxxxx
- Re: PCIe question, Charles, NG
  - Re: PCIe question, Gabor
    - Re: PCIe question, vasile
    - Re: PCIe question, PeteS
    - Re: PCIe question, vasile
    - Re: PCIe question, PeteS
    - Re: PCIe question, Gabor
    - Re: PCIe question, PeteS
OSERDES behavior, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
memory in spartan 3 fpga, selva kumar
- Re: memory in spartan 3 fpga, Nico Coesel
intialize memory in fpga, selva kumar
- Re: intialize memory in fpga, Symon
- Re: intialize memory in fpga, Erik Anderson
- Re: intialize memory in fpga, johnp
Question about xflow?, fl
- Re: Question about xflow?, Duth
Strange behaviour of a design, markus . jank
- Re: Strange behaviour of a design, KJ
  - Re: Strange behaviour of a design, Gabor
- Re: Strange behaviour of a design, MM
  - Re: Strange behaviour of a design, markus . jank
    - Re: Strange behaviour of a design, Gabor
    - Re: Strange behaviour of a design, markus . jank
VHDL core to read/write to Bram_Block., Pablo
- Re: VHDL core to read/write to Bram_Block., Göran Bilski
- Re: VHDL core to read/write to Bram_Block., harshada . pendse
altera's USB byteblaster cable: anyone has the mindford one?, Rodo
- Re: altera's USB byteblaster cable: anyone has the mindford one?, Fredrik
  - Re: altera's USB byteblaster cable: anyone has the mindford one?, Rodo
Problems with PLB_DDR2 core and soft reset, JimboD2
- Re: Problems with PLB_DDR2 core and soft reset, vsurducan@xxxxxxxxx
  - Re: Problems with PLB_DDR2 core and soft reset, JimboD2
    - Re: Problems with PLB_DDR2 core and soft reset, Jeff Cunningham
    - Re: Problems with PLB_DDR2 core and soft reset, PrestonMc
VGA controller in the EDK ?, Simon
- Re: VGA controller in the EDK ?, John Williams
  - Re: VGA controller in the EDK ?, Simon
    - Re: VGA controller in the EDK ?, Mark McDougall
    - Re: VGA controller in the EDK ?, Simon
PCB Layers, maxascent
- Re: PCB Layers, Gabor
  - Re: PCB Layers, vsurducan@xxxxxxxxx
  - Re: PCB Layers, Ben Jackson
- Re: PCB Layers, vt2001cpe
- Re: PCB Layers, John Larkin
  - Re: PCB Layers, maxascent
    - Re: PCB Layers, vsurducan@xxxxxxxxx
- Re: PCB Layers, Symon
  - Re: PCB Layers, Gabor
    - Re: PCB Layers, vasile
    - Re: PCB Layers, Symon
    - Re: PCB Layers, Symon
- Re: PCB Layers, comp.arch.fpga
  - Re: PCB Layers, vsurducan@xxxxxxxxx
Xilinx Virtex IOB Regiters and Noise???, Analog_Guy
- Re: Xilinx Virtex IOB Regiters and Noise???, John_H
- Re: Xilinx Virtex IOB Regiters and Noise???, Gabor
  - Re: Xilinx Virtex IOB Regiters and Noise???, Analog_Guy
    - Re: Xilinx Virtex IOB Regiters and Noise???, John Retta
Re: New keyword 'orif' and its implications, Symon
- Re: New keyword 'orif' and its implications, Weng Tianxiang
  - Re: New keyword 'orif' and its implications, Symon
    - Re: New keyword 'orif' and its implications, Weng Tianxiang
    - Re: New keyword 'orif' and its implications, Jonathan Bromley
VHDL clocking scheme VS Verilog clocking scheme, anilcelebi
- Re: VHDL clocking scheme VS Verilog clocking scheme, Jonathan Bromley
  - Re: VHDL clocking scheme VS Verilog clocking scheme, Gabor
    - Re: VHDL clocking scheme VS Verilog clocking scheme, Jonathan Bromley
XHWIF interface for Virtex II devices, shadabambat1@xxxxxxxxx
weird issue on Xilinx ML501/ML505 evkit designs, vasile
PLL Power and m/n ratio, fpgabuilder
- Re: PLL Power and m/n ratio, austin
  - Re: PLL Power and m/n ratio, Gabor
- Re: PLL Power and m/n ratio, Paul Leventis
  - Re: PLL Power and m/n ratio, fpgabuilder
    - Re: PLL Power and m/n ratio, Gabor
Re: ANNC: FPGA Noise Fundamentals Webcast, MikeShepherd564
- Re: ANNC: FPGA Noise Fundamentals Webcast, Gabor
tricking bitgen into creating rom-like behavior, mittra
- Re: tricking bitgen into creating rom-like behavior, glen herrmannsfeldt
  - Re: tricking bitgen into creating rom-like behavior, Andy
    - Re: tricking bitgen into creating rom-like behavior, Sean Durkin
- Re: tricking bitgen into creating rom-like behavior, PFC
bidirectional pin help, Zorjak
- Re: bidirectional pin help, MM
  - Re: bidirectional pin help, Zorjak
    - Re: bidirectional pin help, Jeff Cunningham
    - Re: bidirectional pin help, Zorjak
    - Re: bidirectional pin help, Mike Treseler
    - Re: bidirectional pin help, Zorjak
    - Re: bidirectional pin help, MM
    - Re: bidirectional pin help, Zorjak
    - Re: bidirectional pin help, MM
    - Re: bidirectional pin help, Zorjak
    - Re: bidirectional pin help, MM
    - Re: bidirectional pin help, Zorjak
    - Re: bidirectional pin help, MM
    - Re: bidirectional pin help, MM
    - Re: bidirectional pin help, Zorjak
Interview Questions, onenanometer@xxxxxxxxx
- Re: Interview Questions, Nir Dahan
Looking for VME-Bus Core, Christian Kirschenlohr
Partial reconfiguration using ICAP, ajith.thamara@xxxxxxxxx
- Re: Partial reconfiguration using ICAP, Sean Durkin
  - Re: Partial reconfiguration using ICAP, ajith.thamara@xxxxxxxxx
- Re: Partial reconfiguration using ICAP, Neil Steiner
Newbie with ISE 9_2_02i_lin gets error : Process "Translate" failed, Bob Smith
- Re: Newbie with ISE 9_2_02i_lin gets error : Process "Translate" failed, manolete
  - Re: Newbie with ISE 9_2_02i_lin gets error : Process "Translate" failed, Joseph Samson
  - Re: Newbie with ISE 9_2_02i_lin gets error : Process "Translate" failed, Bob Smith
[xilinx ise simulation] how to keep all settings between runs, Bart van Deenen
- Re: how to keep all settings between runs, Duth
  - Re: how to keep all settings between runs, Bart van Deenen
    - Re: how to keep all settings between runs, Duth
Overriding a VHDL generic for command-line driven synthesis with ISE, Uncle Noah
A beginner asks questions about synthesis under Xilinx XST, tersono
- Re: A beginner asks questions about synthesis under Xilinx XST, svenand
  - Re: A beginner asks questions about synthesis under Xilinx XST, tersono
Implementing MIPS Memory Hiarchy, Roman Zeilinger
- Re: Implementing MIPS Memory Hiarchy, Jon Beniston
  - Re: Implementing MIPS Memory Hiarchy, Roman Zeilinger
    - Re: Implementing MIPS Memory Hiarchy, Jon Beniston
hwicap for EDK 9.1, Kevin
Dynamic power estimation using Xpower, mahshid
- Re: Dynamic power estimation using Xpower, Symon
  - Re: Dynamic power estimation using Xpower, mahshid
Samtec PowerPoser power filtering solution., Symon
- Re: Samtec PowerPoser power filtering solution., Gabor
  - Re: Samtec PowerPoser power filtering solution., Symon
    - Re: Samtec PowerPoser power filtering solution., PeteS
    - Re: Samtec PowerPoser power filtering solution., Symon
xilinx impact 9.2 problem, Rutger Stoots
- Re: xilinx impact 9.2 problem, Gabor
  - Re: xilinx impact 9.2 problem, Rutger Stoots
    - Re: xilinx impact 9.2 problem, Jon Elson
    - Re: xilinx impact 9.2 problem, Rutger Stoots
    - Re: xilinx impact 9.2 problem, Nitro
    - Re: xilinx impact 9.2 problem, Rutger Stoots
OCM BRAM and PCC issues..., xenix
DDR2 controller V4 vs V5 differences ?, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
- Re: DDR2 controller V4 vs V5 differences ?, Sean Durkin
  - Re: DDR2 controller V4 vs V5 differences ?, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
  - Re: DDR2 controller V4 vs V5 differences ?, John Schmitz
    - Re: DDR2 controller V4 vs V5 differences ?, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
    - Re: DDR2 controller V4 vs V5 differences ?, John Schmitz
    - Re: DDR2 controller V4 vs V5 differences ?, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
Speed test between FPGA and DSP or PC., Pablo
- Re: Speed test between FPGA and DSP or PC., RCIngham
  - Re: Speed test between FPGA and DSP or PC., Hal Murray
- Re: Speed test between FPGA and DSP or PC., comp.arch.fpga
Inout ports in EDK, Koustav
Annoying, Christian Obel
- <Possible follow-ups>
- Annoying, Christian Obel
  - Re: Annoying, John_H
    - Re: Annoying, Uwe Bonnes
    - Re: Annoying, RCIngham
    - Re: Annoying, Gabor
    - Re: Annoying, Mark McDougall
  - Re: Annoying, Gavin Scott
ROUTING=CLOSED in Xilinx 9.1 PR tools, jasuris
- Re: ROUTING=CLOSED in Xilinx 9.1 PR tools, Matthew Hicks
  - Re: ROUTING=CLOSED in Xilinx 9.1 PR tools, jasuris
Altera DDR Controller, Modelsim and Verilog, fpgabuilder
Re: Synthesizing fixed_pkg in ISE 9.2, eli . billauer
- Re: Synthesizing fixed_pkg in ISE 9.2, Andreas Schwarz
  - Re: Synthesizing fixed_pkg in ISE 9.2, Andreas Schwarz
ML365, maxascent
xilinx usb cable question, bert
- Re: xilinx usb cable question, svenand
  - Re: xilinx usb cable question, Bert
    - Re: xilinx usb cable question, morphiend
    - Re: xilinx usb cable question, taco
comparison with embedded processor, bhb
- Re: comparison with embedded processor, Jon Beniston
- Re: comparison with embedded processor, Frank Buss
  - Re: comparison with embedded processor, mmihai
    - Re: comparison with embedded processor, mmihai
how to bidirectional signal in xilinx EDK tool ?, kmk1978
- Re: how to bidirectional signal in xilinx EDK tool ?, Guru
Burst Memory Transfer Request from PPC, lordwolf
- Re: Burst Memory Transfer Request from PPC, Peter Ryser
Power Reduction Strategy, tgschwind
- Re: Power Reduction Strategy, Andy
  - Re: Power Reduction Strategy, Hal Murray
    - Re: Power Reduction Strategy, Andy
    - Re: Power Reduction Strategy, Paul Leventis
- Re: Power Reduction Strategy, Ray Andraka
  - Re: Power Reduction Strategy, Andreas Ehliar
    - Re: Power Reduction Strategy, Peter Alfke
    - Re: Power Reduction Strategy, Jim Granville
    - Re: Power Reduction Strategy, Ray Andraka
- Re: Power Reduction Strategy, Nico Coesel
- Re: Power Reduction Strategy, John Larkin
- Re: Power Reduction Strategy, Jim Granville
Need to force all signals in a design to a known value at start of simulation, wittenjon
- Re: Need to force all signals in a design to a known value at start of simulation, Andy
  - Re: Need to force all signals in a design to a known value at start of simulation, Jonathan Bromley
    - Re: Need to force all signals in a design to a known value at start of simulation, Andy
    - Re: Need to force all signals in a design to a known value at start of simulation, diogratia
    - Re: Need to force all signals in a design to a known value at start of simulation, Jonathan Bromley
    - Re: Need to force all signals in a design to a known value at start of simulation, Andy
- Re: Need to force all signals in a design to a known value at start of simulation, Mike Treseler
- Re: Need to force all signals in a design to a known value at start of simulation, Jonathan Bromley
  - Re: Need to force all signals in a design to a known value at start of simulation, fpgabuilder
ML401 (Virtex 4 development board) as a USB peripheral, alleynb
- Re: ML401 (Virtex 4 development board) as a USB peripheral, John McGrath
  - Re: ML401 (Virtex 4 development board) as a USB peripheral, Hal Murray
    - Re: ML401 (Virtex 4 development board) as a USB peripheral, John McGrath
    - Re: ML401 (Virtex 4 development board) as a USB peripheral, Hal Murray
    - Re: ML401 (Virtex 4 development board) as a USB peripheral, John McGrath
    - Re: ML401 (Virtex 4 development board) as a USB peripheral, alleynb
    - Re: ML401 (Virtex 4 development board) as a USB peripheral, John McGrath
help to sort out the errors, sriman
- Re: help to sort out the errors, ghelbig
  - Re: help to sort out the errors, sriman
Call for Papers: RAAW-2, architect
MicroBlaze and ChipScope, icegray
- Re: MicroBlaze and ChipScope, motty
System Generator Question: Flopping the inputs and outputs, Phil
- Re: System Generator Question: Flopping the inputs and outputs, Phil
Spartan-3A DSP vs. Cyclone III Power-wise, Manny
- Re: Spartan-3A DSP vs. Cyclone III Power-wise, Fredrik
- Re: Spartan-3A DSP vs. Cyclone III Power-wise, austin
  - Re: Spartan-3A DSP vs. Cyclone III Power-wise, rkruger
- Re: Spartan-3A DSP vs. Cyclone III Power-wise, Manny
  - Re: Spartan-3A DSP vs. Cyclone III Power-wise, Paul Leventis
    - Re: Spartan-3A DSP vs. Cyclone III Power-wise, xeinth
    - Re: Spartan-3A DSP vs. Cyclone III Power-wise, austin
help on how to assign data to the function of nios program, sriman
FPL 2007 : Final call for participation, David Thomas
Old issues of XCell magazine, Peter Alfke
- Re: Old issues of XCell magazine, Weng Tianxiang
  - Re: Old issues of XCell magazine, svenand
At what frequencies is it acceptable to generate a clock from a register?, bwilson79@xxxxxxxxx
- Re: At what frequencies is it acceptable to generate a clock from a register?, Duane Clark
- Re: At what frequencies is it acceptable to generate a clock from a register?, KJ
- Re: At what frequencies is it acceptable to generate a clock from a register?, Gabor
- Re: At what frequencies is it acceptable to generate a clock from a register?, Peter Alfke
  - Re: At what frequencies is it acceptable to generate a clock from a register?, bwilson79@xxxxxxxxx
    - Re: At what frequencies is it acceptable to generate a clock from a register?, Peter Alfke
    - Re: At what frequencies is it acceptable to generate a clock from a register?, bwilson79@xxxxxxxxx
    - Re: At what frequencies is it acceptable to generate a clock from a register?, Peter Alfke
    - Re: At what frequencies is it acceptable to generate a clock from a register?, bwilson79@xxxxxxxxx
exe file in modelsim, fazulu deen
- Re: exe file in modelsim, HT-Lab
Re: GPIO_performance, Antti
Multiple MicroBlazes error, young
- Re: Multiple MicroBlazes error, Göran Bilski
Re: Voltage translation question, Gabor
- <Possible follow-ups>
- Re: Voltage translation question, John Larkin
  - Message not available
    - Re: Voltage translation question, John Larkin
    - Message not available
    - Re: Voltage translation question, John Larkin
    - Re: Voltage translation question, Jim Granville
    - Re: Voltage translation question, John Larkin
- Re: Voltage translation question, Brian Drummond
  - Message not available
    - Re: Voltage translation question, Symon
  - Message not available
    - Re: Voltage translation question, Peter Alfke
- Re: Voltage translation question, Jim Granville
MCS -> BIT, LilacSkin
- Re: MCS -> BIT, Antti
  - Re: MCS -> BIT, LilacSkin
    - Re: MCS -> BIT, LilacSkin
    - Re: MCS -> BIT, davide
- Re: MCS -> BIT, Jon Elson
Globally Asynchronous in FPGA, Pasacco
- Re: Globally Asynchronous in FPGA, Symon
  - Re: Globally Asynchronous in FPGA, Pasacco
    - Re: Globally Asynchronous in FPGA, Thomas Stanka
    - Re: Globally Asynchronous in FPGA, Mike Treseler
    - Re: Globally Asynchronous in FPGA, RCIngham
    - Re: Globally Asynchronous in FPGA, David R Brooks
Xilinx / ISE multi-cycle path constraint pitfall, eli . billauer
- Re: Xilinx / ISE multi-cycle path constraint pitfall, Mike Treseler
- Re: Xilinx / ISE multi-cycle path constraint pitfall, John Retta
  - Re: Xilinx / ISE multi-cycle path constraint pitfall, eli . billauer
    - Re: Xilinx / ISE multi-cycle path constraint pitfall, John Retta
    - Re: Xilinx / ISE multi-cycle path constraint pitfall, Mike Treseler
    - Re: Xilinx / ISE multi-cycle path constraint pitfall, Ray Andraka
    - Re: Xilinx / ISE multi-cycle path constraint pitfall, Andy
    - Re: Xilinx / ISE multi-cycle path constraint pitfall, Matthew Hicks
    - Re: Xilinx / ISE multi-cycle path constraint pitfall, Jonathan Bromley
    - Re: Xilinx / ISE multi-cycle path constraint pitfall, Mike Treseler
    - Re: Xilinx / ISE multi-cycle path constraint pitfall, John Retta
    - Re: Xilinx / ISE multi-cycle path constraint pitfall, Mike Treseler
    - Re: Xilinx / ISE multi-cycle path constraint pitfall, eli . billauer
    - Re: Xilinx / ISE multi-cycle path constraint pitfall, Mike Treseler
    - Re: Xilinx / ISE multi-cycle path constraint pitfall, Symon
    - Re: Xilinx / ISE multi-cycle path constraint pitfall, eli . billauer
    - Re: Xilinx / ISE multi-cycle path constraint pitfall, Symon
    - Re: Xilinx / ISE multi-cycle path constraint pitfall, eli . billauer
    - Re: Xilinx / ISE multi-cycle path constraint pitfall, Symon
    - Re: Xilinx / ISE multi-cycle path constraint pitfall, eli . billauer
    - Re: Xilinx / ISE multi-cycle path constraint pitfall, Symon
    - Re: Xilinx / ISE multi-cycle path constraint pitfall, Symon
    - Re: Xilinx / ISE multi-cycle path constraint pitfall, eli . billauer
    - Re: Xilinx / ISE multi-cycle path constraint pitfall, Mike Treseler
- Re: Xilinx / ISE multi-cycle path constraint pitfall, mk
- Re: Xilinx / ISE multi-cycle path constraint pitfall, Symon
Re: EDK 9.1.02i warnings flood, JD Newcomb
DDR controller - best device to perform, pgw
- Re: DDR controller - best device to perform, Nico Coesel
  - Re: DDR controller - best device to perform, Peter Alfke
    - Re: DDR controller - best device to perform, pgw
    - Re: DDR controller - best device to perform, Nico Coesel
    - Re: DDR controller - best device to perform, PeteS
  - Re: DDR controller - best device to perform, pgw
  - Re: DDR controller - best device to perform, PeteS
    - Re: DDR controller - best device to perform, fpgabuilder
    - Re: DDR controller - best device to perform, PeteS
    - Re: DDR controller - best device to perform, Nico Coesel
    - Re: DDR controller - best device to perform, Tim (one of many)
    - Re: DDR controller - best device to perform, rkruger
    - Re: DDR controller - best device to perform, Daniel S.
- Re: DDR controller - best device to perform, pgw
  - Re: DDR controller - best device to perform, rkruger
Re: Xilinx MIG DDR2 initialization problems, Carson He
help on camera ports, sriman
- Re: help on camera ports, Donald
Xilinx Constraints Question, moogyd
- Re: Xilinx Constraints Question, kenm
- Re: Xilinx Constraints Question, Symon
  - Re: Xilinx Constraints Question, moogyd
    - Re: Xilinx Constraints Question, Symon
Minimal power?, amerdsp
- Re: Minimal power?, Antti
  - Re: Minimal power?, cpope
    - Re: Minimal power?, John_H
- Re: Minimal power?, John_H
Actel APA1000 and JTAG, Niv
- Re: Actel APA1000 and JTAG, Antti
- Re: Actel APA1000 and JTAG, SKatsyuba
Slice equation in bitstream, lembke . stefan
- Re: Slice equation in bitstream, Antti
  - Re: Slice equation in bitstream, lembke . stefan
    - Re: Slice equation in bitstream, Antti
    - Re: Slice equation in bitstream, Symon
    - Re: Slice equation in bitstream, Symon
    - Re: Slice equation in bitstream, lembke . stefan
    - Re: Slice equation in bitstream, lembke . stefan
    - Re: Slice equation in bitstream, Antti
    - Re: Slice equation in bitstream, Symon
    - Re: Slice equation in bitstream, lembke . stefan
- Re: Slice equation in bitstream, Symon
  - Re: Slice equation in bitstream, lembke . stefan
iMPACT command for selecting remote host running CableServer?, Marcel van de Burgwal
FIFO16 on virtex4 error?, Chao
- Re: FIFO16 on virtex4 error?, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
- Re: FIFO16 on virtex4 error?, bruce_hw_guy
  - Re: FIFO16 on virtex4 error?, Peter Alfke
    - Re: FIFO16 on virtex4 error?, Chao
Reconfiguring a Virtex4 DCM_ADV., Symon
- Re: Reconfiguring a Virtex4 DCM_ADV., davide
  - Re: Reconfiguring a Virtex4 DCM_ADV., Symon
    - Re: Reconfiguring a Virtex4 DCM_ADV., young
Routing JTAG pins thru FPGA, vu3rdd
- Re: Routing JTAG pins thru FPGA, Andrew Holme
  - Re: Routing JTAG pins thru FPGA, vu3rdd
    - Re: Routing JTAG pins thru FPGA, JK
FPGA :'define not allowed in ISE ?, bijoy
- Re: FPGA :'define not allowed in ISE ?, Jon Beniston
Scilab / Matrix, bhb
- Re: Scilab / Matrix, comp.arch.fpga
MGT Link, maxascent
- Re: MGT Link, comp.arch.fpga
- Re: MGT Link, MM
  - Re: MGT Link, maxascent
    - Re: MGT Link, Daniel S.
Fighting with Compact Flash, kron
- Re: Fighting with Compact Flash, Antti
- Re: Fighting with Compact Flash, Mike Treseler
synthesis showing warning (replicated 1 time(s) to handle iob=true attribute.), ankur
- <Possible follow-ups>
- synthesis showing warning (replicated 1 time(s) to handle iob=true attribute.), ankur
  - Re: synthesis showing warning (replicated 1 time(s) to handle iob=true attribute.), Gabor
about mb-gcc error???, kobelai15
- Re: about mb-gcc error???, backhus
- Re: about mb-gcc error???, beeraka@xxxxxxxxx
- Re: about mb-gcc error???, John Williams
DDR2 @ 400 MHz and Xilinx Spartan-3A[N] kits, Tommy Thorn
- Re: DDR2 @ 400 MHz and Xilinx Spartan-3A[N] kits, John_H
  - Re: DDR2 @ 400 MHz and Xilinx Spartan-3A[N] kits, Tommy Thorn
- Re: DDR2 @ 400 MHz and Xilinx Spartan-3A[N] kits, Eric Crabill
  - Re: DDR2 @ 400 MHz and Xilinx Spartan-3A[N] kits, Eric Crabill
    - Re: DDR2 @ 400 MHz and Xilinx Spartan-3A[N] kits, Antti
  - Re: DDR2 @ 400 MHz and Xilinx Spartan-3A[N] kits, Eric Smith
    - Re: DDR2 @ 400 MHz and Xilinx Spartan-3A[N] kits, Eric Crabill
Mico32 bootloader, Richard Klingler
Virtex 4 IBUFG to DCM routing question, MikeJ
- Re: Virtex 4 IBUFG to DCM routing question, austin
  - Re: Virtex 4 IBUFG to DCM routing question, austin
  - Re: Virtex 4 IBUFG to DCM routing question, MikeJ
    - Re: Virtex 4 IBUFG to DCM routing question, Jim Wu
    - Re: Virtex 4 IBUFG to DCM routing question, Symon
    - Re: Virtex 4 IBUFG to DCM routing question, MikeJ
    - Re: Virtex 4 IBUFG to DCM routing question, MikeJ
    - Re: Virtex 4 IBUFG to DCM routing question, Jim Wu
    - Re: Virtex 4 IBUFG to DCM routing question, MikeJ
ChipHit: ASIC, FPGA, EDA Search Engine, ted
- Re: ChipHit: ASIC, FPGA, EDA Search Engine, RCIngham
- Re: ChipHit: ASIC, FPGA, EDA Search Engine, yttrium
- Re: ChipHit: ASIC, FPGA, EDA Search Engine, Symon
  - Re: ChipHit: ASIC, FPGA, EDA Search Engine, ted
Multiplication Problem on Microblaze Software, mfgunes
- Re: Multiplication Problem on Microblaze Software, Jon Beniston
  - Re: Multiplication Problem on Microblaze Software, mfgunes
    - Re: Multiplication Problem on Microblaze Software, Göran Bilski
    - Re: Multiplication Problem on Microblaze Software, RCIngham
    - Re: Multiplication Problem on Microblaze Software, Martin Thompson
    - Re: Multiplication Problem on Microblaze Software, mfgunes
    - Re: Multiplication Problem on Microblaze Software, mfgunes
    - Re: Multiplication Problem on Microblaze Software, Göran Bilski
    - Re: Multiplication Problem on Microblaze Software, mfgunes
    - Re: Multiplication Problem on Microblaze Software, Göran Bilski
    - Re: Multiplication Problem on Microblaze Software, mfgunes
    - Re: Multiplication Problem on Microblaze Software, Göran Bilski
    - Re: Multiplication Problem on Microblaze Software, mfgunes
    - Re: Multiplication Problem on Microblaze Software, Göran Bilski
    - Re: Multiplication Problem on Microblaze Software, mfgunes
    - Re: Multiplication Problem on Microblaze Software, mfgunes
Xilinx PACKER warning bout carry, Brad Smallridge
- Re: Xilinx PACKER warning bout carry, Alan Nishioka
  - Re: Xilinx PACKER warning bout carry, Brad Smallridge
    - Re: Xilinx PACKER warning bout carry, Mike Treseler
    - Re: Xilinx PACKER warning bout carry, Brad Smallridge
    - Re: Xilinx PACKER warning bout carry, Mike Treseler
- Re: Xilinx PACKER warning bout carry, Andy
  - Re: Xilinx PACKER warning bout carry, Brad Smallridge
- Re: Xilinx PACKER warning bout carry, Mike Treseler
  - Re: Xilinx PACKER warning bout carry, Brad Smallridge
    - Re: Xilinx PACKER warning bout carry, Mike Treseler
    - Re: Xilinx PACKER warning bout carry, Brad Smallridge
System ACE failure on ML405, Kunal
- Re: System ACE failure on ML405, Torsten Landschoff
- Re: System ACE failure on ML405, comp.arch.fpga
  - Re: System ACE failure on ML405, Kunal
How to save simulation results in Xilinx ISE ?, Telenochek
- Re: How to save simulation results in Xilinx ISE ?, Duth
Xilinx DDR2 SDRAM controller performance, bruce_hw_guy
- Re: Xilinx DDR2 SDRAM controller performance, Andrew Burnside
  - Re: Xilinx DDR2 SDRAM controller performance, bruce_hw_guy
    - Re: Xilinx DDR2 SDRAM controller performance, Nico Coesel
Delaying a pulse train, m
- Re: Delaying a pulse train, Peter Alfke
  - Re: Delaying a pulse train, m
    - Re: Delaying a pulse train, Peter Alfke
    - Re: Delaying a pulse train, John_H
    - Re: Delaying a pulse train, m
    - Re: Delaying a pulse train, Jim Granville
    - Re: Delaying a pulse train, Peter Alfke
    - Re: Delaying a pulse train, m
    - Re: Delaying a pulse train, Jim Granville
    - Re: Delaying a pulse train, m
    - Re: Delaying a pulse train, Peter Alfke
    - Re: Delaying a pulse train, m
    - Re: Delaying a pulse train, Jim Granville
    - Re: Delaying a pulse train, Peter Alfke
    - Re: Delaying a pulse train, nospam
    - Re: Delaying a pulse train, Jim Granville
    - Re: Delaying a pulse train, John_H
    - Re: Delaying a pulse train, Jim Granville
    - Re: Delaying a pulse train, Jim Granville
- Re: Delaying a pulse train, John_H
- Re: Delaying a pulse train, lb . edc
SDRAM Controller, maxascent
- Re: SDRAM Controller, Gabor
Xilinx Spartan FPGA : Strange Errors, moogyd
- Re: Xilinx Spartan FPGA : Strange Errors, ghelbig
- Message not available
  - Re: Xilinx Spartan FPGA : Strange Errors, moogyd
- <Possible follow-ups>
- Xilinx Spartan FPGA : Strange Errors, moogyd
  - Re: Xilinx Spartan FPGA : Strange Errors, Symon
Virtex4+PPC+ext. RAM: Problems generating ACE files (solved!?), Torsten Landschoff
xst fails..., Matthias Alles
- Re: xst fails..., Jon Beniston
  - Re: xst fails..., Gerhard Hoffmann
    - Re: xst fails..., Matthias Alles
  - Re: xst fails..., Matthias Alles
    - Re: xst fails..., Brian Drummond
    - Re: xst fails..., Matthias Alles
mixed Verilog/VHDL in ispLever 7.0 broken, Richard Klingler
- Re: mixed Verilog/VHDL in ispLever 7.0 broken, Jon Beniston
  - Re: mixed Verilog/VHDL in ispLever 7.0 broken, Richard Klingler
SATA OOB using Rocket IO (Virtex 5), mkumarsampath
edk + spi, u_stadler@xxxxxxxx
- Re: edk + spi, Antti
  - Re: edk + spi, u_stadler@xxxxxxxx
new xilinx forums, Antti
Virtex-4 router failures when trying to mux multiple clocks (WARNING:Route:438), bwilson79@xxxxxxxxx
- Re: Virtex-4 router failures when trying to mux multiple clocks (WARNING:Route:438), Gabor
  - Re: Virtex-4 router failures when trying to mux multiple clocks (WARNING:Route:438), bwilson79@xxxxxxxxx
    - Re: Virtex-4 router failures when trying to mux multiple clocks (WARNING:Route:438), Gabor
Using Virtex-II Pro MGT with external CDR, jeff . johnson . au
Design Behavior affected by use of Chipscope, MNiegl
- Re: Design Behavior affected by use of Chipscope, John Retta
  - Re: Design Behavior affected by use of Chipscope, MNiegl
Problems using xilfatfs on XUP V2Pro board, Philip Potter
- Re: Problems using xilfatfs on XUP V2Pro board, Siva Velusamy
  - Re: Problems using xilfatfs on XUP V2Pro board, Philip Potter
Xilinx 13th August opportunity, Antti
- Re: Xilinx 13th August opportunity, Jon Beniston
- Re: Xilinx 13th August opportunity, Jim Granville
  - Re: Xilinx 13th August opportunity, Antti
    - Re: Xilinx 13th August opportunity, jacobusn@xxxxxxxxxx
    - Re: Xilinx 13th August opportunity, KJ
    - Re: Xilinx 13th August opportunity, Peter Alfke
    - Re: Xilinx 13th August opportunity, Antti
edk+uclinux ??? <about make dep>, kobelai15
- Re: edk+uclinux ??? <about make dep>, Gerhard Hoffmann
- Re: edk+uclinux ??? <about make dep>, kobelai15
- Re: edk+uclinux ??? <about make dep>, backhus
  - Re: edk+uclinux ??? <about make dep>, RODWILL
regarding the clock issues in the fpga..., ekavirsrikanth@xxxxxxxxx
- Re: regarding the clock issues in the fpga..., John_H
  - Re: regarding the clock issues in the fpga..., ekavirsrikanth@xxxxxxxxx
    - Re: regarding the clock issues in the fpga..., John_H
LUT distributed memory in FPGA devices, tlenomade
- Re: LUT distributed memory in FPGA devices, Peter Alfke
- Re: LUT distributed memory in FPGA devices, austin
  - Re: LUT distributed memory in FPGA devices, tlenomade
Used Stratix II FPGA's, eswar . saladi
ucf editor edk, u_stadler@xxxxxxxx
- Re: ucf editor edk, Zara
Re: How to locate the internal state machine in timing simulation, John_H
- <Possible follow-ups>
- Re: How to locate the internal state machine in timing simulation, John Retta
  - Message not available
    - Re: How to locate the internal state machine in timing simulation, John Retta
- Re: How to locate the internal state machine in timing simulation, John_H
  - Message not available
    - Re: How to locate the internal state machine in timing simulation, John_H
- Re: How to locate the internal state machine in timing simulation, David Binnie
Webpack 9.1 and Samba, Peter C. Wallace
- Re: Webpack 9.1 and Samba, ghelbig
  - Re: Webpack 9.1 and Samba, Peter Wallace
embedded tips, ed . agunos
- Re: embedded tips, austin
  - Re: embedded tips, IDDLife
- Re: embedded tips, svenand
Xilinx Xilfatfs SystemACE library and partition format, antoine . vernay
Amount of wire and logic, Pasacco
- Re: Amount of wire and logic, Zara
  - Re: Amount of wire and logic, Pasacco
    - Re: Amount of wire and logic, Peter Alfke
    - Re: Amount of wire and logic, Symon
    - Re: Amount of wire and logic, Frank Buss
    - Re: Amount of wire and logic, Peter Alfke
    - Re: Amount of wire and logic, Frank Buss
    - Re: Amount of wire and logic, Pasacco
    - Re: Amount of wire and logic, Peter Alfke
    - Re: Amount of wire and logic, Matthew Hicks
    - Re: Amount of wire and logic, Matthew Hicks
    - Re: Amount of wire and logic, Peter Alfke
    - Re: Amount of wire and logic, Eric Smith
    - Re: Amount of wire and logic, Peter Alfke
    - Re: Amount of wire and logic, Eric Smith
    - Re: Amount of wire and logic, comp.arch.fpga
    - Re: Amount of wire and logic, Pasacco
    - Re: Amount of wire and logic, Peter Alfke
    - Re: Amount of wire and logic, comp.arch.fpga
    - Re: Amount of wire and logic, Pasacco
    - Re: Amount of wire and logic, Pasacco
    - Re: Amount of wire and logic, Pasacco
    - Re: Amount of wire and logic, Peter Alfke
    - Re: Amount of wire and logic, Markus
    - Re: Amount of wire and logic, Daniel S.
  - Re: Amount of wire and logic, John_H
- Re: Amount of wire and logic, austin
DDR/DDR2 controller - core, pgw
- Re: DDR/DDR2 controller - core, dimtsios@xxxxxxxxxxxxx
  - Re: DDR/DDR2 controller - core, pgw
- Re: DDR/DDR2 controller - core, Nico Coesel
  - Re: DDR/DDR2 controller - core, pgw
    - Re: DDR/DDR2 controller - core, Nico Coesel
- Re: DDR/DDR2 controller - core, Andrew Burnside
  - Re: DDR/DDR2 controller - core, pgw
    - Re: DDR/DDR2 controller - core, Andrew Burnside
    - Re: DDR/DDR2 controller - core, RCIngham
    - Re: DDR/DDR2 controller - core, Daniel S.
EDK (XPS) - Path problem causing "Generate Libraries and BSPs" to fail..., PretzelX
Re: EDK speed issue, John Williams
SystemACE, xilfatfs and feof(), Philip Potter
Reset and DCM, danielgutierrezcastro
- Re: Reset and DCM, austin
  - Re: Reset and DCM, Barry
spartan3 picoblaze how to make .bmm file work, Bart van Deenen
- mem file, Bart van Deenen
- Re: spartan3 picoblaze how to make .bmm file work, svenand
  - Re: spartan3 picoblaze how to make .bmm file work, Bart van Deenen
- got it!, Bart van Deenen
- Re: spartan3 picoblaze how to make .bmm file work, Walter Dvorak
secure interfacing between an fpga and a connected device, fpgabuilder
- Re: secure interfacing between an fpga and a connected device, Colin Paul Gloster
  - Re: secure interfacing between an fpga and a connected device, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
    - Re: secure interfacing between an fpga and a connected device, fpgabuilder
    - Re: secure interfacing between an fpga and a connected device, comp.arch.fpga
    - Re: secure interfacing between an fpga and a connected device, Andreas Schwarz
    - Re: secure interfacing between an fpga and a connected device, PFC
Xilinx Webpack 9.1: How do I export a netlist to another project?, fpga_engineer
- Re: Xilinx Webpack 9.1: How do I export a netlist to another project?, jacobusn@xxxxxxxxxx
  - Re: Xilinx Webpack 9.1: How do I export a netlist to another project?, Brian Drummond
what the AC exactly short for here..., neil3w@xxxxxxxxx
High Speed ADC, Clement
- Re: High Speed ADC, comp.arch.fpga
  - Re: High Speed ADC, Joe
    - Re: High Speed ADC, comp.arch.fpga
Specifying LVDS I/O's in Xilinx FPGA's, moogyd
- Re: Specifying LVDS I/O's in Xilinx FPGA's, Symon
- Re: Specifying LVDS I/O's in Xilinx FPGA's, John_H
- Re: Specifying LVDS I/O's in Xilinx FPGA's, John Retta
- Re: Specifying LVDS I/O's in Xilinx FPGA's, moogyd
Write of 64 from PowerPC to my IP conected to the PLB?, ferorcue
- Re: Write of 64 from PowerPC to my IP conected to the PLB?, Alan Nishioka
  - Re: Write of 64 from PowerPC to my IP conected to the PLB?, comp.arch.fpga
  - Re: Write of 64 from PowerPC to my IP conected to the PLB?, ferorcue
    - Re: Write of 64 from PowerPC to my IP conected to the PLB?, comp.arch.fpga
- Re: Write of 64 from PowerPC to my IP conected to the PLB?, Eric Smith
- Re: Write of 64 from PowerPC to my IP conected to the PLB?, Guru
Exception handling code in the OR1200, IDDLife
- Re: Exception handling code in the OR1200, IDDLife
Mico32, Richard Klingler
Ph.D in France, M Ihsan Baig
Regional Clock Resources, Aida
- Re: Regional Clock Resources, El Mehdi Taileb
New Xilinx forum., Symon
- Re: New Xilinx forum., austin
  - Re: New Xilinx forum., DJ Delorie
    - Re: New Xilinx forum., austin
    - Re: New Xilinx forum., Sylvain Munaut
  - Re: New Xilinx forum., Jim Granville
    - Re: New Xilinx forum., austin
  - Re: New Xilinx forum., comp.arch.fpga
  - Re: New Xilinx forum., comp.arch.fpga
    - Re: New Xilinx forum., austin
    - Re: New Xilinx forum., KJ
    - Re: New Xilinx forum., Peter Alfke
    - Re: New Xilinx forum., Peter Alfke
    - Re: New Xilinx forum., austin
  - Re: New Xilinx forum., Barry
    - Re: New Xilinx forum., austin
  - Re: New Xilinx forum., Nico Coesel
  - Re: New Xilinx forum., Antti
    - Re: New Xilinx forum., mk
    - Re: New Xilinx forum., Antti
    - Re: New Xilinx forum., John_H
    - Re: New Xilinx forum., Antti
  - Re: New Xilinx forum., Tommy Thorn
- Re: New Xilinx forum., Tommy Thorn
  - Re: New Xilinx forum., austin
- Re: New Xilinx forum., John_H
- Re: New Xilinx forum., Jim Granville
  - Re: New Xilinx forum., Ken Ryan
- Re: New Xilinx forum., kempaj
  - Re: New Xilinx forum., Symon
  - Re: New Xilinx forum., Mike Treseler
    - Re: New Xilinx forum., Peter Alfke
    - Re: New Xilinx forum., David Binnie
    - Re: New Xilinx forum., Antti
    - Re: New Xilinx forum., Antti
    - Re: New Xilinx forum., austin
  - Re: New Xilinx forum., Colin Paul Gloster
    - Re: New Xilinx forum., Mike Treseler
    - Re: New Xilinx forum., Colin Paul Gloster
    - Re: New Xilinx forum., Gabor
Microblaze GPIO interrupt, markmcmahon
- Re: Microblaze GPIO interrupt, John Williams
EDK 8.1, echo
- Re: EDK 8.1, John_H
  - Re: EDK 8.1, echo
    - Re: EDK 8.1, Ed McGettigan
    - Re: EDK 8.1, echo
TEMAC Performance Issues with Virtex 4FX, ryufrank
- Re: TEMAC Performance Issues with Virtex 4FX, PFC
  - Re: TEMAC Performance Issues with Virtex 4FX, ryufrank
    - Re: TEMAC Performance Issues with Virtex 4FX, PFC
  - Re: TEMAC Performance Issues with Virtex 4FX, ryufrank
    - Re: TEMAC Performance Issues with Virtex 4FX, Sylvain Munaut
    - Re: TEMAC Performance Issues with Virtex 4FX, morphiend
    - Re: TEMAC Performance Issues with Virtex 4FX, ryufrank
    - Re: TEMAC Performance Issues with Virtex 4FX, PFC
  - Re: TEMAC Performance Issues with Virtex 4FX, John Williams
    - Re: TEMAC Performance Issues with Virtex 4FX, Guru
    - Re: TEMAC Performance Issues with Virtex 4FX, ryufrank
    - Re: TEMAC Performance Issues with Virtex 4FX, Torsten Landschoff
Re: Can multiple Ferrite Beads be used to connect ...?, commone
- Re: Can multiple Ferrite Beads be used to connect ...?, Symon
  - Re: Can multiple Ferrite Beads be used to connect ...?, commone
    - Re: Can multiple Ferrite Beads be used to connect ...?, Symon
    - Re: Can multiple Ferrite Beads be used to connect ...?, commone
    - Re: Can multiple Ferrite Beads be used to connect ...?, Symon
    - Re: Can multiple Ferrite Beads be used to connect ...?, John_H
    - Re: Can multiple Ferrite Beads be used to connect ...?, commone
Digilent USB module linux, Andreas Gauckler
- Re: Digilent USB module linux, Guenter Dannoritzer
FPGA board connected to CMOS chip: ESD hazards?, EEngineer
- Re: FPGA board connected to CMOS chip: ESD hazards?, Andy Botterill
- Re: FPGA board connected to CMOS chip: ESD hazards?, austin
  - Re: FPGA board connected to CMOS chip: ESD hazards?, EEngineer
    - Re: FPGA board connected to CMOS chip: ESD hazards?, Symon
    - Re: FPGA board connected to CMOS chip: ESD hazards?, austin
AREA_GROUP Map Error, Matthew Hicks
- Re: AREA_GROUP Map Error, Matthew Hicks
Problem about clock switch in Quartus II 6.0, X.Y.
- Re: Problem about clock switch in Quartus II 6.0, Mike Treseler
- Re: Problem about clock switch in Quartus II 6.0, dkarchmer
  - Re: Problem about clock switch in Quartus II 6.0, X.Y.
    - Re: Problem about clock switch in Quartus II 6.0, dkarchmer
Exciting openings for Standard Cell libraries/Memory designer in a fortune 50 organisation, Nitin Gupta
Need suggestion for my project, IDDLife
- Re: Need suggestion for my project, Antti
- Re: Need suggestion for my project, randomdude
- Re: Need suggestion for my project, austin
  - Re: Need suggestion for my project, John_H
    - Re: Need suggestion for my project, IDDLife
    - Re: Need suggestion for my project, Antti
    - Re: Need suggestion for my project, IDDLife
xilinx plb_ddr to self refresh mode, cpope
- Re: xilinx plb_ddr to self refresh mode, svenand
- Re: xilinx plb_ddr to self refresh mode, svenand
new to the group, jitendra
- Re: new to the group, Antti
- Re: new to the group, John Adair
  - Re: new to the group, svenand
DSP design into FPGA, sriman
how to test the FPGA on the board, archana
- Re: how to test the FPGA on the board, makhan
Re: Single Ended signal in sync with V5 GTP, Marc Randolph
- <Possible follow-ups>
- Re: Single Ended signal in sync with V5 GTP, Sylvain Munaut
bidirectional pin, Zorjak
- Re: bidirectional pin, Matthew Hicks
  - Re: bidirectional pin, Zorjak
    - Re: bidirectional pin, Matthew Hicks
    - Re: bidirectional pin, Jeff Cunningham
- Re: bidirectional pin, Iwo Mergler
  - Re: bidirectional pin, EEngineer
- Re: bidirectional pin, Eric Smith
  - Re: bidirectional pin, Zorjak
FPGA accelerator service, drop669
- Re: FPGA accelerator service, davem
OpenSPARC, drop669
- Re: OpenSPARC, Antti
  - Re: OpenSPARC, drop669
    - Re: OpenSPARC, Matthew Hicks
bare bone PCI cards with FPGAs, fpgauser
- Re: bare bone PCI cards with FPGAs, Jeremy Harris
Confused about my behavioral simulation under ISE 9.1, bob . zigon
- Re: Confused about my behavioral simulation under ISE 9.1, Matthew Hicks
  - Re: Confused about my behavioral simulation under ISE 9.1, John Retta
Area report, ZHI
- Re: Area report, nezhate
- Re: Area report, John McCaskill
  - Re: Area report, ZHI
mb-gdb: problem simulating memory mapped i/o devices, manuel-lozano
xps error never seen before: google reveals nothing; help!, N.V. Chandramouli
- Re: xps error never seen before: google reveals nothing; help!, Torsten Landschoff
  - Re: xps error never seen before: google reveals nothing; help!, N.V. Chandramouli
- Re: xps error never seen before: google reveals nothing; help!, Alan Nishioka
  - Re: xps error never seen before: google reveals nothing; help!, N.V. Chandramouli
EDK =>"Virtex4_PPC_Example_9_1" on ubuntu, not able to change LEDs blinking through minicom hyperterminal, N.V. Chandramouli
- <Possible follow-ups>
- EDK =>"Virtex4_PPC_Example_9_1" on ubuntu, not able to change LEDs blinking through minicom hyperterminal, N.V. Chandramouli
SDR SDRAM controller for Xilinx Spartan-3E, Eli Billauer
- Re: SDR SDRAM controller for Xilinx Spartan-3E, Mike Treseler
  - Re: SDR SDRAM controller for Xilinx Spartan-3E, Eli Billauer
    - Re: SDR SDRAM controller for Xilinx Spartan-3E, jacobusn@xxxxxxxxxx
- Re: SDR SDRAM controller for Xilinx Spartan-3E, Guru
- Re: SDR SDRAM controller for Xilinx Spartan-3E, Martin Thompson
  - Re: SDR SDRAM controller for Xilinx Spartan-3E, Eli Billauer
    - Re: SDR SDRAM controller for Xilinx Spartan-3E, PFC
    - Re: SDR SDRAM controller for Xilinx Spartan-3E, Guru
    - Re: SDR SDRAM controller for Xilinx Spartan-3E, Georg Acher
    - Re: SDR SDRAM controller for Xilinx Spartan-3E, PFC
    - Re: SDR SDRAM controller for Xilinx Spartan-3E, Georg Acher
    - Re: SDR SDRAM controller for Xilinx Spartan-3E, Antonio Pasini
    - Re: SDR SDRAM controller for Xilinx Spartan-3E, Guru
- Re: SDR SDRAM controller for Xilinx Spartan-3E, Andy Peters
  - Re: SDR SDRAM controller for Xilinx Spartan-3E, ghelbig
Re: How to choose FPGA for a huge computation?, Ray Andraka
- Re: How to choose FPGA for a huge computation?, fpga_toys
camera module interface to FPGA, sriman
- Re: camera module interface to FPGA, David Binnie
Spartan 3E starter kit DDR SDRAM, fpgauser
- Re: Spartan 3E starter kit DDR SDRAM, Tommy Thorn
  - Re: Spartan 3E starter kit DDR SDRAM, jacobusn@xxxxxxxxxx
    - Re: Spartan 3E starter kit DDR SDRAM, jacobusn@xxxxxxxxxx
    - Re: Spartan 3E starter kit DDR SDRAM, fpgauser
    - Re: Spartan 3E starter kit DDR SDRAM, fpgauser
V4FX PPC suspend/resume, cpope
- Re: V4FX PPC suspend/resume, austin
  - Re: V4FX PPC suspend/resume, Matthew Hicks
    - Re: V4FX PPC suspend/resume, austin
  - Re: V4FX PPC suspend/resume, cpope
    - Re: V4FX PPC suspend/resume, Peter Ryser
Download the contents of the FPGA's RAM block, EEngineer
- Re: Download the contents of the FPGA's RAM block, fpgauser
  - Re: Download the contents of the FPGA's RAM block, EEngineer
    - Re: Download the contents of the FPGA's RAM block, makhan
    - Re: Download the contents of the FPGA's RAM block, EEngineer
    - Re: Download the contents of the FPGA's RAM block, Matthew Hicks
    - Re: Download the contents of the FPGA's RAM block, makhan
Forwarding engines, Richard Klingler
Altera-Xilinx interfacing SERDES transcievers problem, vasile
- Re: Altera-Xilinx interfacing SERDES transcievers problem, jjohnson
  - Re: Altera-Xilinx interfacing SERDES transcievers problem, vasile
- Re: Altera-Xilinx interfacing SERDES transcievers problem, dimtsios@xxxxxxxxxxxxx
V4 DSOCM always reads back zeroes, Jeff Cunningham
- Re: V4 DSOCM always reads back zeroes, Jeff Cunningham
Re: Aldec ActiveHDL vs. ModelSim, Ray Andraka
Re: Corgen Adder Vs DSP48 Adder in Virtex4, Ray Andraka
- Re: Corgen Adder Vs DSP48 Adder in Virtex4, Matthew Hicks
Inputs as an Array in Verilog??, eromlignod
- Re: Inputs as an Array in Verilog??, Jonathan Bromley
Re: hard_temac : mdio conflict, Brian Drummond
Position at The MathWorks, Ali
DOSFS for EDK, jcr_alr
- Re: DOSFS for EDK, Antti
- Re: DOSFS for EDK, Antti
Writing data to bram with microblaze, mfgunes
- Re: Writing data to bram with microblaze, svenand
Re: Altera or Xilinx, Paul Leventis
- Re: Altera or Xilinx, Peter Alfke
- Re: Altera or Xilinx, Stef
- <Possible follow-ups>
- Re: Altera or Xilinx, FBergemann
- Re: Altera or Xilinx, Wei Wang
- Re: Altera or Xilinx, Ray Andraka
  - Re: Altera or Xilinx, fpga_toys
Re: Best CPU platform(s) for FPGA synthesis, Paul Leventis
- <Possible follow-ups>
- Re: Best CPU platform(s) for FPGA synthesis, MM
Re: Interesting problems about high performance computing, glen herrmannsfeldt
Re: regarding RTOS in NIOS II, PretzelX
Re: V5 compared to V2P, austin
Re: Looking for PLD with embedded memory, Evan Lavelle
- Re: Looking for PLD with embedded memory, Philipp Klaus Krause
  - Re: Looking for PLD with embedded memory, Eric Smith
Static Timing Analysis Using Primetime for FPGAs, ctaniguchi1
- Re: Static Timing Analysis Using Primetime for FPGAs, Mike Lewis
  - Re: Static Timing Analysis Using Primetime for FPGAs, ctaniguchi1
    - Re: Static Timing Analysis Using Primetime for FPGAs, dkarchmer
    - Re: Static Timing Analysis Using Primetime for FPGAs, jjohnson
    - Re: Static Timing Analysis Using Primetime for FPGAs, Evan Lavelle
    - Re: Static Timing Analysis Using Primetime for FPGAs, Mike Treseler
    - Re: Static Timing Analysis Using Primetime for FPGAs, Evan Lavelle
    - Re: Static Timing Analysis Using Primetime for FPGAs, Mike Treseler
- Re: Static Timing Analysis Using Primetime for FPGAs, Jon Beniston
- Re: Static Timing Analysis Using Primetime for FPGAs, Mike Treseler
  - Re: Static Timing Analysis Using Primetime for FPGAs, Paul Leventis
    - Re: Static Timing Analysis Using Primetime for FPGAs, Tommy Thorn
    - Re: Static Timing Analysis Using Primetime for FPGAs, Paul Leventis
help on basics of ethernet interface, sriman
Xilinx Webpack for Linux 64 bit?, Christopher Cole
- Re: Xilinx Webpack for Linux 64 bit?, davide
- Re: Xilinx Webpack for Linux 64 bit?, ghelbig
- Re: Xilinx Webpack for Linux 64 bit?, Eric Smith
Re: VCD file doesn't show anything in GtkWave, bybell
- Re: VCD file doesn't show anything in GtkWave, davem
Re: completely open source fpga toolchain, Totally_Lost
Fatal Error ISE 9.1, martin . leibetseder
- Re: Fatal Error ISE 9.1, davide
  - Re: Fatal Error ISE 9.1, johnp
Re: DDR Simulation Model, Sebastian Goller
- Re: DDR Simulation Model, PFC
- Re: DDR Simulation Model, Kevin Neilson
- <Possible follow-ups>
- Re: DDR Simulation Model, Sebastian Goller
- Re: DDR Simulation Model, Sebastian Goller
  - Re: DDR Simulation Model, PFC
  - Re: DDR Simulation Model, Brian Drummond
    - Re: DDR Simulation Model, Sebastian Goller
    - Re: DDR Simulation Model, Sebastian Goller
    - Re: DDR Simulation Model, Brian Drummond
    - Re: DDR Simulation Model, Sebastian Goller
Slow PSDONE when using variable phase shift with a Spartan3E 500 (stepping 1), Dolphin
- Re: Slow PSDONE when using variable phase shift with a Spartan3E 500 (stepping 1), Georg Acher
  - Re: Slow PSDONE when using variable phase shift with a Spartan3E 500 (stepping 1), Dolphin
    - Re: Slow PSDONE when using variable phase shift with a Spartan3E 500 (stepping 1), Dolphin
    - Re: Slow PSDONE when using variable phase shift with a Spartan3E 500 (stepping 1), Georg Acher
    - Re: Slow PSDONE when using variable phase shift with a Spartan3E 500 (stepping 1), Dolphin
- Re: Slow PSDONE when using variable phase shift with a Spartan3E 500 (stepping 1), John_H
  - Re: Slow PSDONE when using variable phase shift with a Spartan3E 500 (stepping 1), Dolphin
Re: ASIC Digital Design Blog, michel . talon
- <Possible follow-ups>
- Re: ASIC Digital Design Blog, Kunal
- Re: ASIC Digital Design Blog, Tommy Thorn
  - Re: ASIC Digital Design Blog, Nir Dahan
Re: Xilinx/ModelSim bug ? Clocking headache ..., Sylvain Munaut
- <Possible follow-ups>
- Re: Xilinx/ModelSim bug ? Clocking headache ..., Mike Treseler
  - Re: Xilinx/ModelSim bug ? Clocking headache ..., Brian Drummond
- Re: Xilinx/ModelSim bug ? Clocking headache ..., Andy
  - Re: Xilinx/ModelSim bug ? Clocking headache ..., Georg Acher
    - Re: Xilinx/ModelSim bug ? Clocking headache ..., Mike Treseler
    - Re: Xilinx/ModelSim bug ? Clocking headache ..., Erik Widding
    - Re: Xilinx/ModelSim bug ? Clocking headache ..., Mike Treseler
Altera Cyclone II and Cyclone III "distributed" RAM?, Ioiod
- Re: Altera Cyclone II and Cyclone III "distributed" RAM?, Ben Twijnstra
- Re: Altera Cyclone II and Cyclone III "distributed" RAM?, Tommy Thorn
  - Re: Altera Cyclone II and Cyclone III "distributed" RAM?, Paul Leventis
Xilinx Webpack 9.2 and Windows 2000 Pro?, Ioiod
- Re: Xilinx Webpack 9.2 and Windows 2000 Pro?, HT-Lab
  - Re: Xilinx Webpack 9.2 and Windows 2000 Pro?, jacobusn@xxxxxxxxxx
    - Re: Xilinx Webpack 9.2 and Windows 2000 Pro?, ghelbig
    - Re: Xilinx Webpack 9.2 and Windows 2000 Pro?, Eric Smith
    - Re: Xilinx Webpack 9.2 and Windows 2000 Pro?, Brian Drummond
    - Re: Xilinx Webpack 9.2 and Windows 2000 Pro?, Laurent Pinchart
    - Re: Xilinx Webpack 9.2 and Windows 2000 Pro?, Duane Clark