Re: Best CPU platform(s) for FPGA synthesis
- From: Matthieu <m.a.t.t.h.i.e.u.m.i.c.h.o.n@xxxxxxxxxxx>
- Date: Mon, 30 Jul 2007 11:37:39 +0900
PFC wrote:
3 GB is a practical limit because the PCI bus and other memory-mapped
devices typically occupy some hundred megabytes of address space. So you
can't use this memory space to access RAM.
These are usually not mapped into the address space of a user process.
Nope, but the (32-bit) kernel needs to see the mmap'ed peripherals + the userspace RAM if implementation of stuff like file reading, etc is to be efficient (without juggling with pages)...
Anandtech ran an article which does quite a good job in explaining the 2 and 3 GB barriers.
http://www.anandtech.com/gadgets/showdoc.aspx?i=3034
.
- References:
- Re: Best CPU platform(s) for FPGA synthesis
- From: Andreas Hofmann
- Re: Best CPU platform(s) for FPGA synthesis
- From: comp.arch.fpga
- Re: Best CPU platform(s) for FPGA synthesis
- From: PFC
- Re: Best CPU platform(s) for FPGA synthesis
- Prev by Date: Odelay usage in virtex5
- Next by Date: Re: Odelay usage in virtex5
- Previous by thread: Re: Best CPU platform(s) for FPGA synthesis
- Next by thread: Restricting XST parameter widths from .mpd files?
- Index(es):
Relevant Pages
|
|