Re: dual port ram

Jonathan Bromley wrote:
On Sat, 28 Jul 2007 18:02:28 +0100, Andy Botterill
<andy@xxxxxxxxxxxxxxxxxxxxx> wrote:


Ah. I was intending to use the dual port ram as a register file. The register file needs 3 registers (out of 18-20) initialising at reset. Is there any way to do this using any of the dual/single port RAM's?


See below - in FPGAs, yes. In other technologies, no. For this problem on this scale, the technique I usually
use is to build the DPRAM in the ordinary way, and then to build a regular collection of flip-flops with one FF per RAM location.
These FFs are reset to 0 at power-up, and are changed to 1 whenever the corresponding RAM location is written - an easy
thing to arrange. The trick, of course, is that when you READ
one of the RAM locations you first check the "have I been written" register - and, if it's zero, then you substitute
the desired power-up reset value in place of the RAM contents.

Only three registers need a reset change of state. That will simplify the code. I'll give it a try and get back to you.

HOWEVER, you *can* initialise the contents of any Xilinx
RAM at configuration (I think - betcha there are some exceptions I don't know about). Trawl the docs for "memory
initialization file" or somesuch. Plenty of people here will
have that information at their fingertips; I don't.

Hopefully I won't have to use this method.

Thanks for everyones help.
.

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