Re: 1ms delay in V5 FPGA
On Jul 16, 11:19 am, "RCIngham" <robert.ing...@xxxxxxxxx> wrote:
That should work. Make sure you clear the counter on entry to the waiting
state. It is good practice to exit on "greater than or equal to" rather
than "equal to" despite the former using slightly more combinatorial logic
resources.
Better yet, set the count to whatever period you need immediately
prior to entering the waiting state, and wait for it to go to zero by
checking the carry bit out of the decrementer (down counter).
Andy
.
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