Re: Analogue like signal interaction within cpld possible ????

Ulrich Bangert wrote:
Gents,

please allow me to confront you with some strange timing behaviour which I
have measured with an Xilinx XC95108 cpld.

Consider two well conditioned clock signals of 10 MHz (both having EXACTLY
the same frequency) entering the cpld. Inside the cpld each clock signal is
divided by 4 by means of two d-flip-flops. The two resulting 2.5 Mhz signals
enter an exclusive-or-gate which delivers an output signal where the
pulse/pause-relationship directly depends on the phase relationship of the
two input clocks.

If some of you feel reminded to something that you have seen before: Yes,
basically this is the principle of an so called linear phase comparator
which has been used to compare high stability clocks (for example cesium
clocks) against each other before high resolution time interval counters
like the HP5370 or the Stanford Research SR620 were available.

Now imagine one of the two clocks is de-tuned by exactly 0.001 Hz. It is a
bit beyond the discussion HOW this is achieved but you may believe me that
this is possible and that THIS is not part of the discussed problem. Now the
phase relationship of the clocks changes slowly in time as does the
pulse/pause relationship behind the xor gate. The pulse/pause relationship
of the xor's output can be measured by two completely different methods:

a) by generating an dc voltage which is directly proportional to the
pulse/pause relationship (again a bit tricky if you want it to be an really
high resolution measurement, but it can be done)

b) by directly measuring the output pulse width with an high resolution time
interval counter like the SR620 having a 25 ps single shot resolution for
time interval measurements.

It is important to note that both methods to measure can be applied at the
same time and that both methods (although based on completely different
physical laws) deliver results that despite some statistical fluctuations
are basically the same. That is why I am pretty sure that what I measure is
really an property of the signal itself and not one of the measurement
apparatus.

If I record the pulse width over time using the two methods and display it
graphically it looks like an pretty linear relationship at the first glance.
If however some math is applied to make it evident how good the linear
relationship really is met then the result is that there are fluctuations in
the pulse width in the order of some +/-450 ps from the expected values.

About these fluctuations the following facts are known:

1) They are not existent in the inputs clocks

2) Expressed in time units as well as expressed as an dc voltage the
fluctuations are orders of magnitude bigger than the resolution and
precision of the time/dc measurement.

3) The fluctuations are by no means of stochastical nature. Instead, If an
positive fluctuation is noticed at an certain phase between the clock
signals, an fluctuation of the same magnitude and sign will be noticed the
next time when the clock signals have the same phase relationship. Or in
other words: The pulse width is an direct function of the phase relationship
of the clocks + an error function which is an direct function of the phase
relationship between the clocks.

How often do you see this, 4 or 8 times per 2.5MHz cycle ?


It seems as if the phase state of one of the signals can have an linear like
modulating effect on the phase state of the second signal (and perhaps vice
versa). Some of you may come to the conclusion that +/-450 ps is not an
number to cause real world troubles but in my case: The whole arrangement
has the intention to measure phase fluctuations of the input clocks that ARE
REALLY THERE but that are smaller at least one order of magnitude than the
noticed errors. And that is why +/-450 ps is an real annoying number for me.

Any hint will be highly appreciated
TIA, Ulrich Bangert

I think I have followed this.
If you are trying to 'zoom into' the phase to high precisons, using
analog Phase integration, there are some rules to follow.

Vcc and Gnd must be VERY clean.
That means no other clocks, and /4 is going to cause more edges and
bounce, plus Vdd impedance noise is usually quite bad on CPLDs.
Any edge that is very close to another, WILL move the threshold, and
so cause phase non-linearities.
Normally, these are so small, well under Tpd, so in the digital domain
they do not matter much. [Some CPLDs will show Tpd delta, vs outputs loded ]

This stuff is NOT on the chip designer's radar :)

So, do not use a CPLD as the Phase Comparitor, but use an LVC Exor gate, preferable with Schmitt. eg LVC1G97, with analog Supply decoupling.

You may even find, you cannot have both non-locked frequencies in the
same package, so may need separate /4 blocks

Also XOR gates will be quite good at 90' output, but will not be linear
at needle pulse phase outputs, so if you need 360' phase with linearity,
I would suggest look at dual quadrature XOR phase comparisons.
(so one is in mid scale, when the other hits the edges)
( or even more phases, 4 would be simple from 10MHz, and use 4 ADC
channels - then 3 of the 4 would be low-error )

-jg

.

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