Re: corgen cic = terrible efficiency?



I'm working with the xilinx corgen cic v3.0. I'm finding that to get a
decent rejection in the images (60 dB) I need about 4 stages. My input is
only 10 bit and I still end up with a 66 bit output, 50 of which are thrown
away. As a result my design won't fit in my device.

If they are truely thrown away, it shouldn't be the cause of why you
aren't fitting into the device.

1. My coregen says it doesn't support V4 for the cic so I've been compiling
for V2. Seems like the DSP48 with the large accumulator is ideal for CICs?

Why do you need DSP48s? Isn't the whole point of a CIC that it doesn't
use multiplies?

2. Looks like the exponential bit growith is from the number of stages.
Since noone uses more than 16 bits at the output why can't the output of the
first integrator be trimmed back to 16 bit before feeding the next and so
on?

Aren't all the integrators cascaded together, then followed by all the
combs?

Cheers,
Jon


.