Re: How to deal with unavoidable setup time violation in CoolRunner II cpld?
- From: Peter Alfke <peter@xxxxxxxxxx>
- Date: Fri, 22 Jun 2007 10:02:07 -0700
The problem with violating set-up time is not the ambiguity of the
output. If the input switches withing that window, then a 0 as an
answer is every bit as good as a 1. Who cares?
The real problem is the increased output delay,if the input changes
during that sub-femtosecond critial part of the set-up time window.
Then the output may fall back at an undefined time after its last
clock.
But modern flip-flops are very fast. A metastable delay of more than 3
ns is extremely rare.
The Xilinx app note is XAPP094 (I think)
You can also google: Metastability, Xilinx, Alfke...
Peter Alfke
On Jun 22, 8:57 am, Iwo Mergler <Iwo.Merg...@xxxxxxxxxxxxxxxxxxxx>
wrote:
cxu...@xxxxxxxxx wrote:
On 6 22 , 10 28 , cxu...@xxxxxxxxx wrote:
Hi,
I apologize if this question is too stupid... basically I want to
build a protocol analyzer with a CoolRunner II cpld. the CPLD will
watch the bus line and extract data. I have passed behaviorial
simulation and fitted the device. but post-fit timing simulation gives
me some setup time violations and the output goes to X afterwards. I
read document that says ASYNC_REG can be used but it is not available
on coolrunner cpld. Then I'm very concerned about what happens in the
real circuit. The bus line will not switch in sync with the sampling
clock, due to different clock domains, jitters etc. what happens in
the real circuit when the setup time is violated? will the cpld go
into metastable state for ever? This must be an old problem that has
been long solved, but how? can anyone help? thanks a lot....
Hsu
Just want to add that I have a local oversampling clock, and the bus
could switch at anytime, say 0.1ns before the clock edge. and the cpld
requires setup time of 1.8ns.
You can't get rid of metastability, but you can reduce it to
spectacularly low likelihoods.
The classic way of doing this is to route the signals through
extra flip-flops. 1-2 are usually enough for most applications.
Violating the setup time on the first FF gives you a certain
chance of it entering a metastable state. It won't stay in it
forever - it just takes longer to switch. The metastable state
must last longer than the clock period to affect the second FF,
which is very unlikely.
The critical setup time windows which could cause a problem are in
the sub-femtosecond range - somewhere within your setup time window.
I think Xilinx have a appnote somewhere about the details.
Kind regards,
Iwo
.
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