Re: what is the correct way to capture ADC using fpga

On Jun 16, 4:19 pm, John_H <newsgr...@xxxxxxxxxxxxxxxx> wrote:
fpgabuilder wrote:
On Jun 15, 10:18 am, "John_H" <newsgr...@xxxxxxxxxxxxxxxx> wrote:
"cutemonster" <ckh...@xxxxxxxxxxx> wrote in message

news:CuOdneSaAIBJXO_b4p2dnAA@xxxxxxxxxxxxxxx

Whatever you do, please don't use the DCM to generate the clock for the ADC
since it could raise the noise floor of the ADC output significantly.
Instead, use the clean clock that feeds the ADC to run the FPGA.

- John_H

I am curious as to know the reason behind not using fpga generated
clock to drive the adc. Is it because they have higher amount of
jitter? I am in the process of designing a datapath from adc to the
fpga.

Thanks.
-sanjay

The jitter is the problem. For a high speed ADC, the error from jitter
can approach the ratio of the jitter to the clock period for a properly
band-limited input signal. For a direct IF sampling system, the error
can exceed that ratio. If you think of the voltage slewing on the ADC
input, the error in the sample point corresponds directly in a voltage
error; if the sample was ideally zero volts, the jitter makes the actual
sample further up or down that rapidly changing voltage.

The noise floor will be noticeably raised in a fast system. The
cleanest way to work with an FPGA/ADC system is to use the clean clock
to drive the ADC and the FPGA, no daisy chaining. If you *must* use an
FPGA to drive the clock (if you're doing phase modulation of the
sampling, for instance) then a cleanup PLL is required to get the noise
down to an acceptable level.

FPGAs are superb for logic. They are not designed to function as analog
elements. The DCMs are well specified and perform very well for even
the most demanding logic. But DCMs are not analog quality. Treat them
as analog noise sources! The jitter is the biggest issue.

- John_H

Thanks John for this insight. Very helpful. But this has raised some
questions in my mind. Xilinx uses DCMs and they add jitter to the
clocks. On the other hand Altera uses PLLs and they actually filter
out the jitter. So in this case it would be good to go with an Altera
device and drive the clocks to ADC? Or do you see some other problems
as well.

Thanks.
-sanjay

.

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