Re: problems with FSL and Microblaze



On Jun 14, 4:28 pm, FPGA Guy <dmend...@xxxxxxxxx> wrote:
I´m developing a FSL Peripheral. I´m having the following problem:
when trying to generate the bitstream it generates the error:

ERROR:MDT - issued from TCL procedure
"::hw_fsl_v20_v2_10_a::check_syslevel_settings" line 14
fsl_v20_0 (fsl_v20) - FSL_Clk is unconnected.
ERROR:MDT - issued from TCL procedure
"::hw_fsl_v20_v2_10_a::check_syslevel_settings" line 14
fsl_v20_1 (fsl_v20) - FSL_Clk is unconnected.

Looking at the system.mhs file I found:

BEGIN fsl_v20
PARAMETER INSTANCE = fsl_v20_0
PARAMETER HW_VER = 2.10.a
END

BEGIN fsl_v20
PARAMETER INSTANCE = fsl_v20_1
PARAMETER HW_VER = 2.10.a
END

But I expected to find something like:

BEGIN fsl_v20
PARAMETER INSTANCE = download_link
PARAMETER HW_VER = 1.00.b
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst
PORT FSL_Clk = sys_clk
END

I suppose this is the problem but I can´t just edit the file because
it seems to be regenerated (missing the ports again) every time I try
to generate the bitstream. Can anyone help me? Thanks

You can edit it when EDK is closed. This file should not be
regenerated if you generate bitstream. I did it a lot.

--Wayne

.



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