Re: Virtex4 CLKX2 DCM Jitter

"Gerhard Hoffmann" <spamtrap@xxxxxxxx> wrote in message
On Wed, 06 Jun 2007 07:35:13 -0700, austin <austin@xxxxxxxxxx> wrote:

The extra pins to ground isn't go to do anything for him (use of IOs as
ground), as he is already in an excellent package in V4, and we are
looking at his bypassing solution. He used all one value for Vcco
bypass, 0402 1.0uF, and I am working on showing him that there can be
anti-resonant peaks (right around 200 MHz), where the use of all one
value is a bad choice.

Using a different mix of caps will only produce different resonances.

I recently had some time to wait for while (1) { XST; translate; map;
place & route }
and used it to play with capacitors.

6.8 Mb pdf of capacitors on a stripline: pictures and impedance plots,
still bound to grow.


(hi, Peter, see you at the Berlin XFest!)

regards, Gerhard

Hi Gerhard,
Thanks for posting that. A very interesting series of experiments. They show
how both form factor and layout are important.
I wonder if you saw the thread back in March about X2Y caps? Subject,
"Bypass caps, X2Y and 'puddles'". You may like to check it out, there are
links to some similar experiments there also.

FWIW, I think all this different value caps thing is bunkum. Especially if
they're in the same sized package. Unless someone does a detailed 3-D
analysis _INCLUDING_ the bond wire, the BGA pacakge traces and the BGA
balls, I won't be convinced by 'resonance' bluster. OTOH, the X2Y stuff has
me convinced that I should think even harder about bypass networks in my
next design.
Thanks, Syms.
p.s. I guess it would be fairly straightforward for Mike (the OP) to change
some values in his bypass network and see how it affects jitter. That'd be


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