Re: How to Find false path in a design

VIPS wrote:

We have been knowing the false path and its nature but i am confused
as to how to identify a false path in a design having say 100 modules.
We know that false path as defination that it is the path that is
never executed or sanitisized henceforth it is not included in the
STA . But the million dollar question is if the design is really big
the how can one it so as to name it in the synthesis. I want to know
the steps followed in the industry.

I use separate modules for each clock domain
and run STA on those. I use "known good"
synchronization techniques between the modules.

-- Mike Treseler