Re: How to Find false path in a design

On Jun 6, 5:07 am, VIPS <thevipulsi...@xxxxxxxxx> wrote:
Hi Guys

We have been knowing the false path and its nature but i am confused
as to how to identify a false path in a design having say 100 modules.
We know that false path as defination that it is the path that is
never executed or sanitisized henceforth it is not included in the
STA . But the million dollar question is if the design is really big
the how can one it so as to name it in the synthesis. I want to know
the steps followed in the industry. I will value your comments and pls
do upload some relevant material or any case study

Thanks in advance

Hi Vips,

If you are not meeting timing and you have lots and lots of path
failing then save yourself some major pain and get a copy of fishtail.
I played with this software some time ago and I can tell you it is
very powerful. You just feed it your rtl and some constraints and out
come a set of SDC files for false and multi-cycle path. On top of that
if can also generate a set of assertions for you to verify the
generated constraints.