Re: How to Find false path in a design
- From: Jonathan Bromley <jonathan.bromley@xxxxxxxxxxxxx>
- Date: Tue, 05 Jun 2007 21:25:46 -0700
On Wed, 06 Jun 2007 04:07:14 -0000,
VIPS <thevipulsinha@xxxxxxxxx> wrote:
We have been knowing the false path and its nature but i am confused[...]
as to how to identify a false path in a design having say 100 modules.
I want to know the steps followed in the industry.
Google for "false path" is a good start. Here's a couple
of places you might look:
PrimeTime, probably the best-known of the many static
timing analysis tools....
http://www.synopsys.com/products/analysis/primetime_ds.html
FishTail, an interesting new tool that uses formal techniques
to identify false and multi-cycle paths....
http://www.fishtail-da.com/
Note, these are not recommendations in any way - just two
products that I happen to be aware of. I'm sure there are
many more. It's not really my field.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@xxxxxxxxxxxxx
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