Re: low speed communication

On 25 Mag, 20:45, austin <aus...@xxxxxxxxxx> wrote:
Andrea,

Since there are no MGT's, you will need to use some IO's from IO banks.

You can use: some number of LVDS 100 ohm differential drivers to
receivers (one direction only, use two sets of buses), a group of single
ended IOs matched to a ribbon cable (with ground, signal, ground,
dignal, this is close to 50 ohms, and can go perhaps 10 meters at the
speed you need).

I suggest the single ended groups, perhaps 8 wires for data, and one
forwarded clock (for nine signals), and a bus like this for each direction.

Clocking these 8 wires at even 10 MHz, would provide 80 Mb/s. At this
slow a rate, you don't really need to clock forward, but I still would
suggest it (along with the data, there is the clock on the ninth wire to
strobe the other end). That way, you don't have to figure out how to
get the clock off of one pcb, and get it to the other one (for a system
synchronous solution).

Just have registers at each end, and create your own (very simple)
protocol. If a "data valid" or "data waiting" signal is needed, just
use another wire. 20 wire ribbon cables are pretty common (ten signal,
ten grounds). Drive the transmit end with something like LVCMOS 8 mA
FAST, which is very close to 50 ohms, and there should be no overshoot,
or undershoot, and the Signal integrity will be good. If that is still
too strong, 6 mA, and even 4 mA drivers can be selected.

The only reason a protocol is required with the MGTs (like aurora:http://www.xilinx.com/products/design_resources/conn_central/grouping...
is that designers need huge bandwidth, and in order to re-synchronize
multiple MGTs (channel bonding), a layer is required to manage all that
stuff.

With a simple parallel interface, you pretty much only need to implement
what you need.

To connect these buses to the 405PPC, you will either have to interface
to the PLB bus, or create an input and output port that is connected to
the 405PPC. Depending on how fancy you want this to be, it could be as
simple as input and output instructions (you create the protocol in
software), or as fancy as a FIFO buffer with DMA into memory mapped into
the 405PPC data memory (the protocol commonly used here is referred to
as "flags placed under a rock" which is a reference to one processor
just waits for a memory location to change, which tells it that the data
it is waiting for is all there, and ready to be read from memory...the
transmitting processor sends all the data, and sets the flag to tell the
receiving processor to pick up the data.

Lots of choices here, and not many "standards" as the task is very
simple, and folks tend to use only what logic they need to in order to
do the job.

Once you pop up to MGTs, there are many more choices, only because there
are more complex interfaces: ethernet, fibre channel, PCIe, etc.....

If you don't need fibre channel, then you don't need media access
controllers (MAC), etc.http://www.xilinx.com/products/design_resources/conn_central/solution...

Austin

Thank you Austin for your reply, I found it very intresting.
I'll search something about your hints over internet and I'll post the
results (and surely other questions).

Just another little question. Why, in your opinion, even Xilinx in its
SPI core doesn't support off-chip Master? SPI peripheral seems to fit
well to my design requrements but it has this huge limitation... I
don't understand why... Any ideas?

.

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