Re: Interfacing DDR RAMs to Virtex 2 Pro on Digilent boards

On May 16, 8:07 am, Brian Drummond <brian_drumm...@xxxxxxxxxxxxx>
wrote:
On Tue, 15 May 2007 16:57:50 -0600, Kevin Neilson

<kevin_neil...@xxxxxxxxxxxxxxxxxxxxx> wrote:
kousta...@xxxxxxxxx wrote:
Hello,

I am graduate student in the Dept. of Computer Sc. & Engg. in
USF.
We are using a Digilent XUP2vpPro board for one of our research
projects. I am trying to interface a Kingston 512 MB DDR RAM in DIMM
to Xilinx virtex 2 Pro FPGA.

You can see what parts are on the DIMM (e.g., Micron, Infineon) and then
figure out what the row size is from that. You can also get good HDL
simulation models from Micron. They are somewhat slow, but accurate.
You instantiate one DRAM model for each DRAM chip on the DIMM.
-Kevin

Following up to second the recommendation on the Micron datasheets and
models, though they seem to omit VHDL models for some newer devices.
Hynix cover that base though.

If you can't find the info you need from Kingston, why not go to
Micron/Crucial for the DIMM itself? Micron fully specify them, and
Crucial sell them online ... I have seen DIMMs with a Micron label on
one side and a Crucial label on the other...

- Brian


Hello Brian,

We are trying to figure ot whether we should go for a
EDK based ucontroller (PPC acting as a memory controller and
interfacing with the other ASIC on FPGA) or generate it with the MIG
based tool. But in any ways I would need simulation libraries/ RTL
models for the DIMM and the DRAMs. As you suggested micron/crucial
libraries would be useful. Can you provide some more information on
these? (links etc). I would appreciate some docs on the DIMM
architecture as well. I have e-mailed Kingston for some specification
docs which lists bank #, column/row address #, and rank organization.
I think I have to get into these details first as well.

Eagerly awaiting a reply.

Thanks,
Koustav

.

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