comp.arch.fpga
- Can't get AREA_GROUP to work,
javaguy11111
- Seeing DCM LOCKED getting asserted in simulation at the same time CLKDV and CLKFX/CLKFX180 begin toggling,
bwilson79@xxxxxxxxx
- Spartan 3E Starter Kit and EDK 8.2,
thomas . b36
- Chain of LUTs is being removed during par,
axr0284
- Ise Flow with PowerPC,
Pablo
- Re: Building Gradually Expertise on VHDL/Verilog Design,
Jeff Cunningham
- 180 differential inputs each 800Mbps using V5,
Test01
- XS40 Download Cable,
raxpeter
- Virtex4 Configuration Problem,
msn444
- Spartan-3E DIG-3E1600 Development Board Kit,
Sandro
- Nexys by Digilen xbd file,
mozilla
- Xilinx CIC core in Spartan 3?,
cs_posting
- Help: Best use of DCM in Spartan-3A?,
Tool
- what is register packing?,
commone
- Inverse of a matrix,
Venkat
- FIR Filter ON FPGA,
bngguy
- spartan-iie,
jonpry
- Xilinx Seminars in Wiesbaden, Berlin, Hannover,
Peter Alfke
- Re: Xilinx Seminars in Wiesbaden, Berlin, Hannover,
Nico Coesel
- Re: Xilinx Seminars in Wiesbaden, Berlin, Hannover,
Peter Alfke
- Re: Xilinx Seminars in Wiesbaden, Berlin, Hannover,
HT-Lab
- Re: Xilinx Seminars in Wiesbaden, Berlin, Hannover,
Peter Alfke
- Re: Xilinx Seminars in Wiesbaden, Berlin, Hannover,
Nico Coesel
- Re: Xilinx Seminars in Wiesbaden, Berlin, Hannover,
austin
- Re: Xilinx Seminars in Wiesbaden, Berlin, Hannover,
HT-Lab
- Re: Xilinx Seminars in Wiesbaden, Berlin, Hannover,
austin
- Re: Xilinx Seminars in Wiesbaden, Berlin, Hannover,
Thomas Heller
- Re: Xilinx Seminars in Wiesbaden, Berlin, Hannover,
u_stadler@xxxxxxxx
- ISE/EDK Kubuntu linux installation issues,
MM
- Xilinx Coregen 2.3 problem,
Vijayant
- Linux device driver for FPGA Xilinx Virtex-4,
greywolf82
- Microchip ICD on FPGA,
fabien.goy@xxxxxxxxx
- How to calculate IFFT based on FFT result?,
Yao Sics
- Re: PacoBlaze 2.2,
Jim Granville
- comp.arch.fpga :How to implement a 128-bit input CRC module in V5,
tylx_wu
- Rodney Smith, long term Altera CEO, dies in accident,
lb . edc
- Quartus-II 7.1 Systemverilog interface?,
Altera User
- JTAG fundamentals question,
Silver
- MPMC2 + flash bootloader problem,
Patrick Dubois
- Is this the correct way to design FPGA to DRAM interface?,
news reader
- Proper word for total delay?,
Slim
- accesing JTAG ports on GPIOs,
maverick
- SignalTap Analyzer...,
Yrjola
- Quartus-II 7.1 Systemverilog support define `` ?,
Xilinx user
- Re: ABC - Actel's PicoBlaze :) - anybody success with coreconsole?,
Vince
- Best way of moving paralell bits of data from over clock domains?,
Daf
- Re: 6502 FPGA core,
Jim Granville
- Re: 6502 FPGA core,
Frank Buss
- Re: 6502 FPGA core,
Jim Granville
- Re: 6502 FPGA core,
spartan3wiz
- Re: 6502 FPGA core,
Frank Buss
- Re: 6502 FPGA core,
spartan3wiz
- Re: 6502 FPGA core,
Jim Granville
- Re: 6502 FPGA core,
Brian Drummond
- Re: 6502 FPGA core,
Jim Granville
- Re: 6502 FPGA core,
Tommy Thorn
- Re: 6502 FPGA core,
Jim Granville
- Re: 6502 FPGA core,
Brian Drummond
- Re: 6502 FPGA core,
Frank Buss
- Re: 6502 FPGA core,
Brian Drummond
- Re: 6502 FPGA core,
Brian Drummond
- Re: 6502 FPGA core,
emu
- <Possible follow-ups>
- Re: 6502 FPGA core,
PeteS
- Spartan3 LVCMOS33 Slew rate,
Test01
- Re: Spartan3 LVCMOS33 Slew rate,
Symon
- Re: Spartan3 LVCMOS33 Slew rate,
austin
- Re: Spartan3 LVCMOS33 Slew rate,
Test01
- Re: Spartan3 LVCMOS33 Slew rate,
austin
- Re: Spartan3 LVCMOS33 Slew rate,
Symon
- Re: Spartan3 LVCMOS33 Slew rate,
Test01
- Re: Spartan3 LVCMOS33 Slew rate,
John Larkin
- Re: Spartan3 LVCMOS33 Slew rate,
austin
- Re: Spartan3 LVCMOS33 Slew rate,
Test01
- Re: Spartan3 LVCMOS33 Slew rate,
Symon
- Re: Spartan3 LVCMOS33 Slew rate,
Test01
- Re: Spartan3 LVCMOS33 Slew rate,
Peter Alfke
- Message not available
- Re: Spartan3 LVCMOS33 Slew rate,
Peter Alfke
- Re: Spartan3 LVCMOS33 Slew rate,
John Larkin
- Re: Spartan3 LVCMOS33 Slew rate,
Test01
- Re: Spartan3 LVCMOS33 Slew rate,
John Larkin
- Re: Spartan3 LVCMOS33 Slew rate,
Test01
- Re: Spartan3 LVCMOS33 Slew rate,
John Larkin
- Re: Spartan3 LVCMOS33 Slew rate,
Newman
- Re: Spartan3 LVCMOS33 Slew rate,
Newman
- Re: Spartan3 LVCMOS33 Slew rate,
Test01
- Re: Spartan3 LVCMOS33 Slew rate,
Newman
- Re: Spartan3 LVCMOS33 Slew rate,
Test01
- Re: Spartan3 LVCMOS33 Slew rate,
John Larkin
- Re: Spartan3 LVCMOS33 Slew rate,
austin
- Re: Spartan3 LVCMOS33 Slew rate,
Jim Granville
- Re: Spartan3 LVCMOS33 Slew rate,
Peter Alfke
- Re: Spartan3 LVCMOS33 Slew rate,
Test01
- Re: Spartan3 LVCMOS33 Slew rate,
Test01
- Re: Spartan3 LVCMOS33 Slew rate,
Test01
EDK9.1: XTemac + LwIP + Xilkernel + unistd.h = possible?,
Ken Ryan
Interfacing EDK application code with Specific BRAMs on FPGA,
koustav79
PC to JTAG,
Matthew Hicks
low speed communication,
Andrea05
ISE 9.1 and ModelSim XE III/Starter 6.2c: Distributed memory behaviorial simulation,
Udo
IOSTANDARD user constrain,
Marlboro
ML505 : beginners problems,
Claire Murphy
Has anyone used Sundance Boards?.,
Pablo
HI EVERYBODY PLEASE.... HELP REGARDING DDR 2 CONTROLLER,
sudhakarmvs
Went from Xilinx to Altera: Cyclone-II and I/O pullup?,
Xilinx user
Testbenches in C driving ISE simulator?,
jesse lackey
VGA signal through breadboard?,
checo
How can I perform Boundary Scan Testing on Altera Cyclone II FPGAs using JTAG?,
futzy . r
Docs on s/w interfacing EDK based design,
koustav79
How to code a bidirectional databus?,
Fed
Actel timing constraints,
Niv (KP)
ModelSim Memory Content import from Intel Hex,
Udo
Dual Core or Quad Core when running Quartus 7.1,
jjlindula@xxxxxxxxxxx
Use BRAM as ROM (Xilinx),
Lancer
Quartus 7.1 segv on recent Linux distributions,
Markus Kuhn
Xilinx 8.2 : Multippass P&R,
moogyd
Ddr sdram feedback pin,
Pablo
How can i command bit Inputs in an FPGA board?,
floris . bala
LVDS termination scheme to nonstandard ribbon cable,
stefan . elmsted
- Re: LVDS termination scheme to nonstandard ribbon cable,
Symon
- Re: LVDS termination scheme to nonstandard ribbon cable,
John_H
- Re: LVDS termination scheme to nonstandard ribbon cable,
austin
- Re: LVDS termination scheme to nonstandard ribbon cable,
Symon
- Re: LVDS termination scheme to nonstandard ribbon cable,
Symon
- Re: LVDS termination scheme to nonstandard ribbon cable,
austin
- Re: LVDS termination scheme to nonstandard ribbon cable,
Symon
- Re: LVDS termination scheme to nonstandard ribbon cable,
austin
- Re: LVDS termination scheme to nonstandard ribbon cable,
John_H
- Re: LVDS termination scheme to nonstandard ribbon cable,
Symon
- Re: LVDS termination scheme to nonstandard ribbon cable,
Brian Davis
- Re: LVDS termination scheme to nonstandard ribbon cable,
John_H
- Re: LVDS termination scheme to nonstandard ribbon cable,
Brian Davis
- Re: LVDS termination scheme to nonstandard ribbon cable,
John_H
- Re: LVDS termination scheme to nonstandard ribbon cable,
austin
- Re: LVDS termination scheme to nonstandard ribbon cable,
Brian Davis
- Re: LVDS termination scheme to nonstandard ribbon cable,
Symon
- Can we move on, please?,
austin
- Re: LVDS termination scheme to nonstandard ribbon cable,
John Larkin
- Re: LVDS termination scheme to nonstandard ribbon cable,
austin
- Re: LVDS termination scheme to nonstandard ribbon cable,
John_H
- Re: LVDS termination scheme to nonstandard ribbon cable,
Symon
- Re: LVDS termination scheme to nonstandard ribbon cable,
Symon
- Re: LVDS termination scheme to nonstandard ribbon cable,
Symon
- Re: LVDS termination scheme to nonstandard ribbon cable,
austin
- Re: LVDS termination scheme to nonstandard ribbon cable,
Symon
- Re: LVDS termination scheme to nonstandard ribbon cable,
austin
- Re: LVDS termination scheme to nonstandard ribbon cable,
John_H
- Re: LVDS termination scheme to nonstandard ribbon cable,
austin
- Re: LVDS termination scheme to nonstandard ribbon cable,
Symon
- Re: LVDS termination scheme to nonstandard ribbon cable,
austin
- Re: LVDS termination scheme to nonstandard ribbon cable,
John Larkin
- Re: LVDS termination scheme to nonstandard ribbon cable,
John_H
- Re: LVDS termination scheme to nonstandard ribbon cable,
John Larkin
- Re: LVDS termination scheme to nonstandard ribbon cable,
Symon
- Re: LVDS termination scheme to nonstandard ribbon cable,
austin
- Re: LVDS termination scheme to nonstandard ribbon cable,
John Larkin
- Re: LVDS termination scheme to nonstandard ribbon cable,
stefan . elmsted
- Re: LVDS termination scheme to nonstandard ribbon cable,
austin
6502 and CPU licences in general,
Frank Buss
Error while generating Libraries and BSPs.,
Shant
SATA OOB detection with Virtex5,
al_ko
fit_timer: trouble connecting interrupt,
Carter De Leo
Custom Memory Initialization,
Alderaan
Altera Cyclone II - used in 100USD Laptop,
Antti
problem while reading from DDR 2 memory,
sudhakarmvs
clarification: clock doubling in Spartan 3,
John Larkin
Binary to BCD,
NA
Project Navigator / Verilog / +define,
johnp
Xilinx ML405 / VxWorks 6.3 Bootloader,
raven
DDR SDRAM in custom board,
Pablo
How the synthesizer acutally works.,
subint
M-RAM allocation in Stratix EPS125B672C6,
nandits11
Design running on board but timing are not met,
J.Ram
LVCMOSS33 I/O sink current,
Test01
Re: Config PROM for Spartan II,
Atmel_PLDs_Rock
JTAG FPGA Debugging,
Silver
how 33-bit BRAM?,
Pasacco
ISE Service pack,
sudarshan . onkar
System-synchronous interface clocking between FPGA's,
bwilson79@xxxxxxxxx
"black_box"-ing of components in toplevel,
L. Schreiber
Problems to simulate (behavioural) in XPS,
ferorcue
Problem with DDR2 controller,
sudhakarmvs
PLB behaviours strangely during burst transactions,
luciorech
Re: FPGA -> SATA?,
Sata Know How
PLB behaviors strangely during burst transactions,
luciorech
using FPGA JTAG as GPIO,
mh
DDR Controller Blue,
Digital Mike
Xilinx doesn't detect setup/hold violations on synchronous reset,
Frai
Atmel release Metal Programmable Cell Fabric uC ARM9,
Jim Granville
How to copy hex data from Quartus vwf file to text?,
Harold
ModelSim version upgrade problem from 6.1c to 6.2c,
Weng Tianxiang
Does FPGA need CPU for processing a packet/frame,
NewToFPGA
SelectIO banking rules,
LilacSkin
Error in NGDBuild,
koustav79
Cyclone FPGAs in Switzerland,
Richard Klingler
Timing not met but working on board,
J.Ram
Filtering the FPGA reset signal,
Eli Bendersky
Support you the best free forum forever !,
f1
AccelDSP Systemgenerator ML403,
eric
Signal Assignment bugs in Quartus-II ... AGAIN!,
edick
Re: How to insert tab in Write() function in VHDL,
Symon
external clock frequency doubles,
Venu
releasing some FPGA tools-ip as open-source,
Antti
EDK 8.1i to EDK 9.1i UCF file errors,
Nju Njoroge
Quartus 7.1 Simulations,
Dan
I need advice,
kemalinmaili@xxxxxxxxx
Single Chip MSX computer full schematic and VHDL sources,
Antti
Precision RTL and DesignWare libraries,
Edmond Coté
Xilinx Timing Constraint Questions,
motty
How to port simulink design to FPGA?,
Bryan
Proper/recommended method for driving clock out from FPGA,
bwilson79@xxxxxxxxx
SystemC and TLM,
confusedpp
video soltion provider,
M Ihsan Baig
Re: Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals.,
glen herrmannsfeldt
Re: 64 bit matrix multplication,
glen herrmannsfeldt
FPGA and LEGO Mindstroms,
Martin Schoeberl
Unusual question about generic port use (optional ports??),
James
Semaphores in xilkernel?,
Pablo
DDR 2 Memory controller own implementattion,
sudhakarmvs
can JTAG port of CPLD gets damaged?,
mohan
too brief documentation?,
Ken Soon
Avnet Virtex-4 LX25 Evaluation Kit,
jrabbani
Avnet Virtex-4 LX Evaluation Kit USB FX2 Issue,
jrabbani
Cyclone II can't enter in configuration mode with EPCS1.,
JaReZ
Cyclone II can't enter configuration mode with EPCS1 active serial.,
JaReZ
seeking insights for potential reconfigurable computing application platforms,
Anne
Mutiple MAC on OPB Bus,
Venu
CML output swing for V5,
Test01
NIOS2 GNU tools under Windows Vista,
alessandro . strazzero
Unable to scan JTAG chain,
mohan
how to delay a signal in virtex FPGA,
michel . talon
clock wide pulse transfer b/w clock domains,
himassk
Global ressource problem,
Amine . Miled
Mind Control and Directed Energy Weapons,
soleilmavis
SERDES question (Lattice ispHSI),
Przemyslaw Wegrzyn
Power Consumption near Timing Failure Point,
Kevin Neilson
- Re: Power Consumption near Timing Failure Point,
austin
- Re: Power Consumption near Timing Failure Point,
Jim Granville
- Re: Power Consumption near Timing Failure Point,
fpga_toys
- Re: Power Consumption near Timing Failure Point,
Paul Leventis
- Re: Power Consumption near Timing Failure Point,
fpga_toys
- Re: Power Consumption near Timing Failure Point,
Paul Leventis
- Re: Power Consumption near Timing Failure Point,
fpga_toys
- Re: Power Consumption near Timing Failure Point,
Paul Leventis
- Re: Power Consumption near Timing Failure Point,
fpga_toys
- Re: Power Consumption near Timing Failure Point,
fpga_toys
- Re: Power Consumption near Timing Failure Point,
Paul Leventis
- Re: Power Consumption near Timing Failure Point,
fpga_toys
- Re: Power Consumption near Timing Failure Point,
glen herrmannsfeldt
- Re: Power Consumption near Timing Failure Point,
Peter Alfke
- Re: Power Consumption near Timing Failure Point,
fpga_toys
- Re: Power Consumption near Timing Failure Point,
Paul Leventis
Interfacing DDR RAMs to Virtex 2 Pro on Digilent boards,
koustav79
Designer,
fpgamark
ise project navigator can't dereference edk pcores from XilinxProcessorIPLib,
L. Schreiber
Using dynamic reconfiguration ports of DCMs on Virtex 4,
emotuk
Xilinx SD-RAM-Controller (Xilinx EDK 8.2)--problems with xil_printf reading from memory,
rmeiche
debit- xilinx bitstream decompiler project has been vanished? or does someone know the URL,
Antti
How low DDR2 Clock Frequency can be? To make it work on FPGA.,
Amit
Xilinx ISE 9.1 Simulator does not work with glibc 2.5,
Thomas Feller
coregen -> simulation error in modelsim,
kislo
Xilinx EDK: Slow OPB write speeds,
Andrew Greensted
reading IDCODE from parallel bus?,
Morten Leikvoll
bus macros for partial reconfiguration of virtex2pro?,
L. Schreiber
Timing constraint question,
Dima
Lockup with Xilinx mch_opb_ddr,
Georg Acher
does SRL exist in non-xilinx FPGAs?,
tlenomade
Anyone using the TimingAnalyzer,
chewie54
Re: Xilinx LogiCore FFT 3.2,
bijoy
Camera Control,
MJ Pearson
Spartan-3A StarterKit, DDR2, WebServer EVERYTHING WORKS, tested ;),
Antti
- Re: Spartan-3A StarterKit, DDR2, WebServer EVERYTHING WORKS, tested ;),
Uwe Bonnes
- Re: Spartan-3A StarterKit, DDR2, WebServer EVERYTHING WORKS, tested ;),
Antti
- Re: Spartan-3A StarterKit, DDR2, WebServer EVERYTHING WORKS, tested ;),
Zara
- Re: Spartan-3A StarterKit, DDR2, WebServer EVERYTHING WORKS, tested ;),
Antti
- Re: Spartan-3A StarterKit, DDR2, WebServer EVERYTHING WORKS, tested ;),
Zara
How to Ask a Question,
Bob Perlman
Digital gain and offset correction,
Marco T.
Re: EDK and Custom Peripheral: error occur when generating bitstream,
Allen
downto usage in EDK,
Manny
plb_tft_cntlr_ref in XUP,
yippeeyang
Power Consumption Estimation for PCI card, any advice?,
commone
- Re: Power Consumption Estimation for PCI card, any advice?,
austin
- Re: Power Consumption Estimation for PCI card, any advice?,
Ben Twijnstra
- Re: Power Consumption Estimation for PCI card, any advice?,
commone
- Re: Power Consumption Estimation for PCI card, any advice?,
austin
- Re: Power Consumption Estimation for PCI card, any advice?,
commone
- Re: Power Consumption Estimation for PCI card, any advice?,
Dave Greenfield
- Re: Power Consumption Estimation for PCI card, any advice?,
austin
- Re: Power Consumption Estimation for PCI card, any advice?,
Paul Leventis
- Re: Power Consumption Estimation for PCI card, any advice?,
austin
- Re: Power Consumption Estimation for PCI card, any advice?,
John_H
- Re: Power Consumption Estimation for PCI card, any advice?,
Paul Leventis
- Re: Power Consumption Estimation for PCI card, any advice?,
Paul Leventis
- Re: Power Consumption Estimation for PCI card, any advice?,
commone
Re: power consumption of integrated circuit in 0.13µm CMOS technology,
Jim Granville
how to choose the perfect fpga support,
kha_vhdl
- Re: how to choose the perfect fpga support,
Peter Alfke
- Re: how to choose the perfect fpga support,
fpga_toys
- Re: how to choose the perfect fpga support,
MM
- Re: how to choose the perfect fpga support,
austin
- Re: how to choose the perfect fpga support,
fpga_toys
- Re: how to choose the perfect fpga support,
kha_vhdl
- Re: how to choose the perfect fpga support,
fpga_toys
- Re: how to choose the perfect fpga support,
fpga_toys
- Re: how to choose the perfect fpga support,
Frank Buss
- Re: how to choose the perfect fpga support,
Robert Ganter
- Re: how to choose the perfect fpga support,
MNiegl
- Re: how to choose the perfect fpga support,
fpga_toys
- Re: how to choose the perfect fpga support,
H. Peter Anvin
- Re: how to choose the perfect fpga support,
fpga_toys
- Re: how to choose the perfect fpga support,
Peter Alfke
- Re: how to choose the perfect fpga support,
Kryten
- Re: how to choose the perfect fpga support,
Eric Smith
- Re: how to choose the perfect fpga support,
Ben Twijnstra
V4FX PPC ICU data transfer timeout?,
jetmarc
Uart problem, xapp223 + Spartan3A,
Borge
xc3sprog and spartan 3e/3a,
mmihai
NgdBuild:604 error,
nezhate
V5 serial link,
Test01
JTAG_SIM_VIRTEX5,
self
Re: ISE9.1: ERROR:Place:911,
Benjamin Todd
Xilinx ISE Simulator 9.1.03i: A bunch of problems (Block Memory Gen.),
Udo
Accessing SRAM on the Spartan-3 Starter Board,
jmariano
Altera enters as second the low-cost multigigabit tranceiver FPGA scene!!,
Antti
Craignell - Spartan-3E DIL Module,
John Adair
Gain and Offset Correction,
Marco T.
Darnaw1 - PGA Spartan-3E Module,
John Adair
DVI over fiber,
AlbertCo
ISE 8.1.03: Bizarre MAP removes almost everything of my design!!!,
yao . sics
How to get 240Mhz clock (8x) using 30Mhz clock input in Virtex4,
fastgreen2000
ISE 9.1 Hierarchy Problem,
networkfabulous
'EVENT (or rising_edge) static prefix requirement....,
Paul
XILINX ISE 9.1i: DELAYCHAIN by input data,
uvbaz
About memory interface generater 007 tool,
Gordon Freeman
ISE : Linux - coregen, compxlib errors,
ashwin
SelectMap or serial: How does the PROM know?,
eli . billauer
ML405 LCD,
Aggie
Xilinx VHDL Attribute syntax error,
Brad Smallridge
Chipscope with custom cable?,
jetmarc
An Open-Source suggestion for Xilinx,
Antti
ISE 8.1,
lorenzo . verardo
Altera FIR Compiler with clock enable,
Wilhelm . Klink
Re: VHDL editing with UltraEdit,
JussiJ
How to add an IP Core to a Quartus project,
benn686
DMA with ipif / user_logic,
berton
sysace and high capacity CF,
zcsizmadia@xxxxxxxxx
License problems with Quartus 7.0 on Linux,
General Schvantzkoph
Ubuntu and Webpack?</